Data Shuffle Circuit for Bad Column Compensation in Memory Arrays
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Solution Overview
Problem
Non-volatile memory systems face challenges in data transfer efficiency due to bad column locations within memory arrays, which can cause signal delays and variability in transistor characteristics, especially as process geometries shrink, leading to increased complexity and area requirements in memory die design.
Innovation Solution
The implementation of data expand and compress circuitry between a bi-directional FIFO and memory arrays, which compensates for bad column locations by packing, unpacking, and aligning data using temporary buffers and selective pipeline stalls, simplifying SERDES design and reducing memory die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transfer is performed through memory arrays with bad column locations, then data transfer rate is reduced due to signal delays and transistor variability, but implementing complex compensation circuits increases device complexity and area
Solution Approach 1:
A data shuffle circuit is introduced as an intermediary component between the memory array and the output interface. This circuit receives data from multiple memory columns, performs shuffling operations to reposition data bytes, and outputs corrected data streams. The shuffle circuit acts as a mediator that compensates for bad column locations without requiring complex modifications to the memory array itself, thereby maintaining data transfer rates while managing device complexity.
Solution Approach 2:
The data transfer path is segmented into distinct functional blocks: memory array, data shuffle circuit, and output interface. The data shuffle circuit is further divided into multiple stages or units that handle different column groups independently. This segmentation allows parallel processing of data from different columns, improving overall data transfer rate while keeping each individual shuffle unit relatively simple in design.
2Manufacturing precision
If process geometries are shrunk to reduce cost per bit, then manufacturing precision improves and cost decreases, but signal delays and transistor characteristic variability increase
Solution Approach 1:
The data shuffle circuit dynamically adjusts data routing based on detected signal quality and column performance characteristics. By changing the routing parameters and data path selections in real-time, the system compensates for variations in transistor characteristics and signal delays caused by process geometry shrinkage, thereby maintaining reliable data transfer despite manufacturing variations.
3Reliability
If data alignment compensation is implemented for bad columns, then data integrity is improved, but additional circuit area is required
Solution Approach 1:
The data shuffle circuit is designed to perform multiple functions: data repositioning, bad column compensation, and data alignment. By making the shuffle circuit multi-functional, the patent avoids adding separate dedicated circuits for each function, thereby improving data integrity through comprehensive compensation while minimizing the additional circuit area required.
Solution Approach 2:
The data shuffle circuit merges data from multiple memory columns into a unified output stream, combining data alignment and bad column compensation functions in a single integrated circuit block. This merging approach improves data integrity through comprehensive error compensation while reducing the total die area compared to implementing separate compensation circuits for each function.
Data Source
AI summary
Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional FIFO may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (SERDES) circuit that drives input/output (I/O) circuitry. The data expand and compress circuitry may pack and unpack data and then align the data passing between the one or more memory arrays and the bi-directional FIFO using a temporary buffer, data shuffling logic, and selective pipeline stalls.