Data Signal Line Drive Circuit Voltage Drop Reduction
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Solution Overview
Problem
Existing data signal line drive circuits in liquid crystal display devices face challenges in reducing voltage drop while maintaining low circuit size, as current techniques either fail to generate sufficient time differences in data capturing timings or result in increased circuit complexity.
Innovation Solution
A data signal line drive circuit configuration with a shift register, first latch portion, and second latch portion, where first latch signals are provided to subsequent second latch circuits, allowing data signal capturing to be split into multiple timings, thereby distributing output timings and reducing voltage drop without increasing circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data capturing is performed simultaneously by all second latch circuits, then high-speed data output is achieved, but voltage drop increases due to simultaneous switching of multiple circuits
Solution Approach 1:
The patent segments the simultaneous data capturing operation into multiple time phases by dividing the second latch circuits into different groups. Each group captures data at different timings controlled by phase-shifted clock signals, thereby distributing the switching current over time and reducing voltage drop while maintaining overall high-speed operation
2Object-affected harmful factors
If delay circuits are added to generate time differences in data capturing timings, then voltage drop is reduced, but circuit size increases
Solution Approach 1:
The patent makes the clock signal serve multiple functions: it simultaneously acts as the timing control signal for phase division and as the operational clock for the latch circuits. By using the same clock signal distributed through different path lengths and buffer configurations, the circuit achieves time differentiation without adding separate delay circuitry, thus avoiding circuit size expansion
3Object-affected harmful factors
If the number of buffer circuits is increased to distribute output timings, then voltage drop is reduced, but device complexity increases
Solution Approach 1:
The patent merges the buffer circuit functionality into the existing clock distribution network by using existing buffer circuits that are already present for clock signal distribution. These existing buffers are repurposed to also control the phase timing of data capturing, thereby achieving output timing distribution without adding extra buffer circuits or increasing device complexity
Data Source
AI summary
A data signal line drive circuit includes: a shift register including a plurality of unit circuits; a first latch portion including a plurality of first latch circuits; and a second latch portion including a plurality of second latch circuits. Here, the k-th (k is a natural number) second latch circuit is provided with first latch signals provided to (k+1)-th and subsequent first latch circuits as a second latch signal, so that the capturing of data signals at the second latch portion is split into two or more timings.