Data Slicer Error Correction for Digital Display Bit-Error Reduction
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Solution Overview
Problem
Existing digital display VBI slicers face high bit-error rates due to signal distortions from noise and channel effects, making it difficult for digital PLLs to lock phases and accurately determine pixel data.
Innovation Solution
A data slicer with an error correction device that includes a subtractor, serial to parallel converters, a level compensator, comparator, co-channel detector, and error bit predictor to generate and output corrected bytes by adjusting slicing levels and detecting co-channel interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital PLL and slicing level estimation are used to determine received data, then the display can distinguish pixel data of each frame, but signal distortions from noise and channel effects cause high bit-error rates
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the slicing level based on signal quality detection. The system monitors signal characteristics and modifies the slicing threshold parameter in response to detected co-channel interference, thereby maintaining accurate data determination despite signal distortions and noise
Solution Approach 2:
The patent implements feedback through a co-channel detector that continuously monitors the received signal and provides information about interference conditions. This feedback loop enables the slicing level estimation to adapt to changing channel conditions, reducing bit-error rates by compensating for signal distortions
2Device complexity
If slicing level is fixed for data determination, then the system structure is simple, but signal distortions cause incorrect determination and high bit-error rates
Solution Approach 1:
The patent applies dynamics by transforming the fixed slicing level into a dynamic parameter that can adjust to signal conditions. The co-channel detector enables the slicing level to vary adaptively based on detected interference, maintaining determination accuracy without requiring complex multi-level slicing structures
Data Source
AI summary
A data slicer includes an error bit predictor, a DC level compensator, a co-channel detector, and an output device. The data slicer generates four bytes according to four slicing levels respectively. The four slicing levels are a DC level, a level generated by adding a predetermined offset to the DC level, a level generated by subtracting the predetermined offset from the DC level, and a compensated level generated by the DC level compensator. The co-channel detector determines if the compensated level has the co-channel interference. The output device generates an output byte according to indication signals generated by the co-channel detector and the error bit predictor and the parity check of the four bytes.