Multi-Mode Data Slicer Thresholding for Fast Warm-Up and Low Noise
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Solution Overview
Problem
Existing automatic gain control (AGC) systems in digital receivers face challenges such as slow acquisition time, continuous current drain, and noise addition due to dual peak detectors, and require complex mixed-mode loops for proper slicing threshold preservation during sleep cycles.
Innovation Solution
A multi-mode threshold generator is introduced, combining a dual peak detector circuit and an R/C circuit with tunable resistors under digital processor control, allowing for fast-attack and low-noise operation while minimizing current consumption and using low-leakage external capacitors to preserve the slicing threshold during sleep cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If dual peak detectors are used to improve acquisition time, then acquisition time is reduced, but continuous current drain and noise addition occur
Solution Approach 1:
The patent implements periodic action by enabling peak detectors only during specific intervals (acquisition phase) and disabling them during other intervals (normal operation and sleep modes). This is achieved through a state machine that transitions between different operational states, activating peak detectors only when needed for threshold acquisition, thereby eliminating continuous current drain and noise while maintaining fast acquisition capability when required.
2Reliability
If mixed-mode loops are used to preserve slicing threshold during sleep cycles, then threshold preservation is achieved, but device complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the complex mixed-mode loop from the system by using a simplified digital state machine approach. Instead of implementing a full mixed-mode feedback loop, the invention uses digital storage elements (flip-flops) and control logic to track receiver state and manage threshold generator selection, thereby achieving threshold preservation during sleep cycles with significantly reduced complexity and cost.
Solution Approach 2:
The patent substitutes the analog mixed-mode loop with a digital state machine implementation. The state machine uses digital logic elements (D-type flip-flops, multiplexers) to control the operation of threshold generators and track receiver states, replacing the continuous analog feedback mechanism with discrete digital control, which reduces complexity while maintaining functionality.
3Loss of time
If fast-attack threshold generators are used to improve warm-up time, then warm-up time is reduced, but noise and current consumption increase
Solution Approach 1:
The patent implements dynamics by making the threshold generator configuration changeable based on operational state. The system dynamically selects between different threshold generator modes (peak detector mode for fast acquisition, R/C circuit mode for low-noise operation) using a state machine that monitors receiver state. This dynamic adaptation allows the system to have fast warm-up when needed while minimizing noise and current consumption during normal operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides fast receiver warm-up, low noise, and low current consumption, offering improved sensitivity and reducing the complexity and cost associated with prior art solutions.
Implementation Method 1
a dual peak detector circuit and an R/C circuit with tunable resistors under digital processor control, allowing for fast-attack and low-noise operation
Implementation Method 2
an R/C circuit with tunable resistors under digital processor control
Implementation Method 3
an R/C circuit with tunable resistors under digital processor control, allowing for fast-attack and low-noise operation
Implementation Method 4
using low-leakage external capacitors to preserve the slicing threshold during sleep cycles
Data Source
AI summary
In an embodiment, set forth by way of example and not limitation, a data slicer includes a signal input node, a comparator having a first input of a first polarity, a second input of a second polarity which is the opposite of the first polarity, and an output coupled to a data out node, the first input of the comparator being coupled to the signal input node, and a multi-mode threshold generator including a first threshold generator and second threshold generator, whereby the first threshold generator is selected firstly and the second threshold generator is selected secondly.