Programmable Data Space Arbiter Priority Override
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional data space arbiters in digital processors are inflexible, often prioritizing the CPU over peripherals, leading to stalling of peripherals even when they need to respond to external events, which can hinder CPU throughput in embedded systems.
Innovation Solution
A programmable data space arbiter that allows secondary bus masters to temporarily elevate their priority above the default CPU priority while maintaining predetermined relationships, using priority override bits in a bus master priority register to dynamically adjust access rights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the CPU is assigned the highest priority in the data space arbiter, then CPU throughput is maximized, but peripheral devices are stalled whenever the CPU accesses memory
Solution Approach 1:
The patent implements dynamic priority assignment by introducing a priority register that allows the CPU priority level to be changed from highest to lowest programmably. This enables the system to switch between CPU-throughput-optimized mode (CPU priority = highest) and peripheral-response-optimized mode (CPU priority = lowest or intermediate), resolving the contradiction between maximizing CPU throughput and allowing peripheral access flexibility.
2Reliability
If a conventional programmable data space arbiter uses predetermined priorities with CPU as highest priority, then CPU access is guaranteed, but peripherals cannot temporarily elevate their priority to respond to external events
Solution Approach 1:
The patent changes the priority parameter programmably by providing a priority register that can set the CPU priority level to highest, intermediate, or lowest. This allows the system to dynamically adjust the CPU's priority parameter based on operational requirements, enabling peripherals to effectively elevate their priority when needed while maintaining CPU access guarantees when CPU performance is critical.
3Adaptability or versatility
If the data space arbiter is made fully programmable to allow any peripheral to have highest priority, then peripheral response flexibility is maximized, but system complexity increases
Solution Approach 1:
The patent applies local quality by providing fine-grained priority control through a priority register where each bit or field can independently control the CPU priority level. This localized control mechanism allows selective adjustment of CPU priority without requiring complete reconfiguration of the entire arbitration logic, reducing the complexity overhead while maintaining high adaptability for peripheral priority management.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data space arbiter is programmable in a non-default mode to raise a priority of any of the secondary bus masters to have a priority higher than the priority of the default bus master while maintaining the predetermined priority relationship to only those secondary bus masters for which the priority level also has been raised above the priority of the default bus master.