Data State Synchronization in Resistance Variable Memory
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Solution Overview
Problem
Resistance variable memory cells experience resistance drift over time, leading to erroneous reading and increased energy consumption in existing data state synchronization methods, particularly in mobile applications where constant power supply is not available.
Innovation Solution
An apparatus and method for data state synchronization that includes a controller configured to perform cleaning operations and generate error correction code parity data, allowing for data inversion within the memory device, reducing erroneous reads and energy consumption by synchronizing data states without tracking drift time or requiring a constant power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data state synchronization is performed by tracking drift time and refreshing cells, then data reliability is improved, but energy consumption increases and constant power supply is required
Solution Approach 1:
The patent applies preliminary action by performing a cleaning operation that places all resistance variable memory cells in a group into a same state (e.g., reset state) before data is written to them. This synchronization of cell states in advance eliminates the need for continuous drift tracking and refreshing, thereby reducing energy consumption while maintaining data reliability. The cleaning operation is performed once when the group of cells is selected, rather than continuously monitoring and refreshing individual cells over time.
2Reliability
If resistance variable memory cells are programmed to target states, then data storage is achieved, but resistance drift causes erroneous sensing over time
Solution Approach 1:
The patent applies preliminary action by performing a cleaning operation that places all resistance variable memory cells in a group into a same state (e.g., reset state) before data is written to them. This synchronization of cell states in advance eliminates the need for continuous drift tracking and refreshing, thereby reducing energy consumption while maintaining data reliability. The cleaning operation is performed once when the group of cells is selected, rather than continuously monitoring and refreshing individual cells over time.
3Reliability
If cleaning operation places all cells in same state, then data state synchronization is achieved, but write operation complexity increases due to data inversion
Solution Approach 1:
The patent applies inversion by determining whether to invert the data pattern based on the target state. When the target state is the set state, the data pattern is inverted before writing, and when the target state is the reset state, the data pattern is written as-is. This inversion strategy simplifies the overall system by allowing the cleaning operation to always target the reset state, and the controller to handle the inversion logic, rather than requiring complex circuitry to directly manipulate cell states.
4Reliability
If existing synchronization methods are used, then erroneous reads are reduced, but mobile applications are limited due to constant power requirement
Solution Approach 1:
The patent applies preliminary action by performing a cleaning operation that places all resistance variable memory cells in a group into a same state (e.g., reset state) before data is written to them. This synchronization of cell states in advance eliminates the need for continuous drift tracking and refreshing, thereby reducing energy consumption while maintaining data reliability. The cleaning operation is performed once when the group of cells is selected, rather than continuously monitoring and refreshing individual cells over time.
Solution Approach 2:
The patent applies periodic action by performing cleaning operations at specific intervals or events (e.g., when a group of cells is selected for writing, or after a predetermined number of write operations). This periodic synchronization maintains data reliability without requiring continuous power supply, making the memory device suitable for mobile applications where power is limited or intermittent.
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.