Data Storage Address Mapping Table for Read Speed
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Solution Overview
Problem
Current data storage apparatuses using memory devices face challenges in improving read performance due to inefficient search operations for read-requested data, leading to degraded read speed and performance.
Innovation Solution
Incorporating a nonvolatile memory device with an address mapping table that stores mapping information between logical and physical addresses, and a processor that generates a modified write logical address by changing a specific bit of the write logical address, allowing for quicker data retrieval by temporarily storing write data and logical addresses in a write buffer and address mapping table.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the entire memory device is scanned to search for read-requested data, then data can be found, but the search time is long and read performance is degraded
Solution Approach 1:
The patent divides the memory device into multiple memory blocks, each with its own address mapping table stored in the RAM. This segmentation allows the search operation to be confined to a specific memory block rather than scanning the entire memory device, significantly reducing search time while maintaining accurate data retrieval.
Solution Approach 2:
The patent pre-loads address mapping tables into the RAM before actual read operations occur. By having the address mapping information readily available in the RAM, the system eliminates the need to scan through the entire memory device during read operations, thus reducing search time without compromising search accuracy.
2Speed
If address mapping table is stored in RAM with modified write logical addresses, then read operation speed is improved, but device complexity increases
Solution Approach 1:
The patent modifies write logical addresses by changing specific bits to create unique identifiers that can be directly stored in the address mapping table. This parameter change allows for faster retrieval during read operations while managing the complexity through systematic address transformation rather than requiring complex mapping algorithms.
3Productivity
If write data is temporarily stored in write buffer, then read performance is improved, but memory resource consumption increases
Solution Approach 1:
The patent uses a write buffer to temporarily store only the address mapping information and modified write logical addresses, rather than storing all write data permanently in the buffer. This partial action approach improves read performance by having address information ready while minimizing memory resource consumption by not unnecessarily retaining all data in the buffer.
Data Source
AI summary
A data storage apparatus includes a nonvolatile memory device, a random-access memory including an address mapping table configured to store mapping information between a logical address received from a host apparatus and a physical address for the nonvolatile memory device, and a processor configured to generate a modified write logical address by changing a value of a specific bit among bits of a write logical address when a write request is received from the host apparatus, and store the modified write logical address in the address mapping table.