Data Stream Flow Controller for SoC Interconnects
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Solution Overview
Problem
Current multiprocessing systems face challenges in providing a cost-effective solution for efficient data transfer between cores in embedded System on-Chip architectures, lacking flexible and efficient interconnection interfaces that support various communication protocols while minimizing complexity and power consumption.
Innovation Solution
A data stream flow controller is introduced, featuring configurable storage for buffering queues, programmable control mechanisms, and additional memory for extended storage, enabling efficient data transfer through interfaces that manage load, store, and push operations, and supporting credit protocols to ensure reliable data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If remote DMA and remote queues solutions are implemented for high performance computing systems, then data transfer efficiency is improved, but cost effectiveness deteriorates in embedded System on-Chip field
Solution Approach 1:
The patent implements flow controllers with configurable storing means that can be selectively enabled or disabled depending on application requirements. These flow controllers use simple FIFO memory structures and basic credit protocol mechanisms that can be implemented with minimal hardware resources, making them suitable for cost-effective embedded SoC designs while still providing improved data transfer efficiency compared to traditional approaches.
Solution Approach 2:
The flow controller includes configurable parameters such as queue depth, buffer size, and credit protocol settings that can be adjusted to optimize performance for different applications. This configurability allows the same hardware structure to adapt to various data transfer requirements without requiring multiple specialized components, thereby maintaining cost-effectiveness while improving productivity.
2Adaptability or versatility
If interconnection interfaces are designed to support full flexibility for various communication protocols, then adaptability is improved, but device complexity increases
Solution Approach 1:
The flow controller is designed as a universal interface that can handle multiple communication protocols and data transfer modes through a single standardized structure. It supports both credit-based flow control and simple FIFO operations, and can interface with different types of processing elements and memory structures, thereby providing protocol flexibility without requiring separate specialized interfaces for each protocol.
Solution Approach 2:
The interface is segmented into distinct functional blocks: a configurable storing means (FIFO), a flow control unit with credit protocol handling, and interface logic. This segmentation allows each component to be independently optimized and configured, reducing overall complexity while maintaining versatility. The modular structure enables selective activation of features based on protocol requirements.
3Speed
If efficient and flexible hardware primitives are implemented, then operation speed is improved, but implementation simplicity deteriorates
Solution Approach 1:
The flow controller implements self-service mechanisms through automatic credit protocol handling and embedded flow control logic. The configurable storing means automatically manages data buffering and forwarding without requiring external intervention, and the credit counters autonomously track and enforce flow control limits. This self-service capability enables high-speed operation while keeping the control logic integrated and relatively simple.
Solution Approach 2:
The flow controller performs preliminary actions by pre-configuring buffer depths, credit limits, and flow control parameters before data transfer begins. The configurable storing means is pre-sized and pre-configured to handle expected data loads, and credit protocols are pre-established to prevent buffer overflows. This preliminary configuration enables high-speed operation without requiring complex runtime decision-making logic.
4Productivity
If multiprocessing architectures are deployed to address complexity and performance capacity, then processing power is improved, but power consumption increases
Solution Approach 1:
The flow controller enables continuous data transfer between processing elements through its buffering and flow control mechanisms. The configurable storing means maintains data flow continuity by buffering data during transient periods, while the credit protocol ensures sustained transfer rates by preventing bottlenecks. This continuity reduces the need for frequent start-stop operations and idle states, thereby improving processing power while minimizing power consumption in multiprocessing architectures.
Data Source
AI summary
A data stream flow-controller controls a transfer of data between a data processing device and an interconnection network. The flow controller includes interfaces for interfacing the controller on the network side and on the processing device side, a configurable storage for buffering queues of data in the controller before transfer to destination, and a programmable controller to control the storage to define queue parameters.