Data Strobe Control Device with Independent Delay Sub-units

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Solution Overview

Problem

In memory systems with multiple memory ranks, existing technologies fail to accurately represent delay values for data strobe signals between the control device and memory devices, leading to reduced data reception margins.

Innovation Solution

A control device with independent data strobe delay values for each memory device within a rank group, allowing for precise adjustment of data strobe signals to improve data reception margins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If training is carried out for just one memory device in a rank group, then the control device complexity is reduced, but the data reception margin is decreased

Engineering Contradiction:
Improvecontrol device complexityVSAvoiddata reception margin
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The control device is divided into multiple sub-units, with each sub-unit corresponding to a specific memory device in the rank group. Each sub-unit independently holds and manages the data strobe delay value for its associated memory device, enabling individualized delay adjustment without increasing overall control device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different data strobe delay values are assigned to different memory devices within the same rank group based on their specific characteristics and positions. This local customization of delay parameters allows each memory device to be optimized independently, improving data reception margin while maintaining a relatively simple control structure.

Inventive Principle:
Principle #3Local quality

2Device complexity

If a single data strobe delay value is used for all memory devices in a rank group, then the device complexity is reduced, but the manufacturing precision of data timing is degraded

Engineering Contradiction:
Improvecontrol device complexityVSAvoiddata timing precision
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The control device architecture is segmented into multiple sub-units, where each sub-unit is responsible for managing the data strobe delay value of a specific memory device. This segmentation allows independent delay value storage and adjustment for each memory device, achieving precise data timing control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces multiple independent data strobe delay values as adjustable parameters, allowing each memory device to have its optimal delay value. This parameter customization enables precise control of data strobe signal timing for each memory device, improving manufacturing precision of data timing.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If independent data strobe delay values are held for each memory device, then the data reception margin is improved, but the device complexity increases

Engineering Contradiction:
Improvedata reception marginVSAvoidcontrol device complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The control device is segmented into multiple sub-units, with each sub-unit corresponding to a specific memory device. Each sub-unit independently holds the data strobe delay value for its associated memory device, enabling individualized delay adjustment while distributing the complexity across modular components rather than concentrating it in a single complex unit.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9368174B2Data strobe control device
Publication Date: 2016.06.14 LONGITUDE LICENSING LTD
  • US9368174B2 patent drawing
  • US9368174B2 patent drawing
  • US9368174B2 patent drawing

AI summary

A control device that comprises a first data strobe input terminal to be connected in common to data strobe terminals that are included respectively in first memory devices, and a plurality of first sub-units each coupled to the first data strobe input terminal and each holding a data strobe delay value corresponding to an associated one of the first memory devices, and the data strobe delay values of the sub-units being independent from each other.