Data Strobe Clock Edge Adjustment for Precise Phase Alignment
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Solution Overview
Problem
Existing semiconductor devices face challenges in maintaining accurate data strobe signal timing due to potential deviations from intermediate potential Vtt, leading to reduced data loading periods or erroneous data transfer.
Innovation Solution
A semiconductor device incorporating a clock generation circuit, clock division circuit with an edge adjustment mechanism, and data strobe output circuit that adjusts the timing of rising and falling edges of internal clock signals to generate complementary data strobe signals with precise phase alignment, without altering the slew rate, thus maintaining signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the drive capability of the output circuit for data strobe signals is adjusted to change the slew rate, then the potentials of the cross points of complementary data strobe signals can be adjusted to match the intermediate potential Vtt, but the signal quality degrades due to changes in signal reflection
Solution Approach 1:
The patent segments the timing adjustment function from the drive capability adjustment. Instead of adjusting the overall drive capability of the output circuit, the invention introduces a separate delay adjustment circuit that selectively delays specific edges (rising or falling) of the clock signal. This segmentation allows timing precision to be improved without affecting the drive capability and signal reflection characteristics of the main output circuit.
Solution Approach 2:
The patent introduces a delay adjustment circuit as an intermediary component between the clock signal source and the data strobe output circuit. This intermediary selectively applies delay to specific edges of the clock signal without altering the drive capability of the main output circuit, thereby achieving timing adjustment while maintaining signal quality. The delay adjustment circuit acts as a mediator that decouples the timing adjustment function from the drive capability adjustment.
2Reliability
If the timing of rising and falling edges of internal clock signals is adjusted to achieve precise phase alignment of data strobe signals, then accurate data transfer is ensured, but the device complexity increases due to additional edge adjustment circuits
Solution Approach 1:
The patent applies local quality by making the delay adjustment selective rather than uniform. The delay adjustment circuit selectively delays only the rising edge or only the falling edge of the clock signal based on specific timing requirements, rather than applying uniform delay to all edges. This selective local adjustment achieves the necessary phase alignment while minimizing the addition of circuit complexity compared to a comprehensive timing adjustment system.
Solution Approach 2:
The patent introduces dynamic adjustability to the clock division circuit through the delay adjustment circuit. The circuit can dynamically select which edge (rising or falling) requires delay adjustment based on timing measurements and requirements. This dynamic capability allows the circuit to adapt to different timing conditions without requiring multiple fixed configurations, thereby managing complexity while maintaining reliability.
3Stability of the object's composition
If the period of complementary data strobe signals is kept constant despite different rising and falling edge times, then accurate data loading timing is maintained, but the potentials of cross points may deviate from intermediate potential Vtt leading to timing errors
Solution Approach 1:
The patent implements feedback by measuring the actual potentials of the cross points of complementary data strobe signals and using this information to adjust the timing of rising and falling edges through the delay adjustment circuit. The system continuously monitors the cross point potentials and makes corrective timing adjustments to ensure they match the intermediate potential Vtt, thereby maintaining both period stability and potential accuracy simultaneously.
Solution Approach 2:
The patent changes the timing parameters (delay of rising or falling edges) of the internal clock signal based on the measured cross point potentials. By dynamically adjusting these timing parameters through the delay adjustment circuit, the system ensures that the cross points occur at the correct intermediate potential Vtt while maintaining the constant period requirement, thus resolving the contradiction between period stability and potential accuracy.
Data Source
AI summary
A semiconductor device includes: a clock generator generating a first internal clock signal based on an external clock signal; a clock divider generating second and third internal clock signals based on the first internal clock signal and including an edge adjustor adjusting a timing of one of rising and falling edges of the third internal clock signal, an adjustment information holder supplying an edge adjustment signal to the edge adjustor, and a data strobe generator receiving the second and third internal clock signals to generate a first data strobe signal based on the second internal clock signal, and a second data strobe signal with a phase different from that of the first data strobe signal, based on the third internal clock signal. The edge adjustor adjusts the timing of at least one of the rising and falling edges of the third internal clock signal based on the edge adjustment signal.