Data Strobe Gate Signal Circuit for Asynchronous Memory Reads
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Solution Overview
Problem
The asynchronous nature of the clock signal from the processor and the data strobe signal from the memory in different clock domains can lead to incorrect data reading due to phase differences, causing issues in data extraction during read operations.
Innovation Solution
A data strobe gate signal generator circuit is implemented in the processor, comprising a selector circuit and a feedback circuit, which uses counting values from both signals to generate an enable signal, allowing for accurate extraction of the data strobe signal and subsequent accurate data reading from the memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor extracts the data strobe signal using its own clock signal, then the data reading operation can proceed, but the asynchronous nature of different clock domains causes phase differences leading to incorrect data reading
Solution Approach 1:
The patent introduces a data strobe gate signal generator circuit as an intermediary component between the processor clock domain and the memory data strobe signal. This circuit generates a gate signal that synchronizes the asynchronous clock domains, allowing accurate extraction of data strobe signals without direct conflict between different clock frequencies and phases
Solution Approach 2:
The patent employs a feedback mechanism where the data strobe gate signal generator monitors the phase relationship between the processor clock signal and the memory data strobe signal, and dynamically adjusts the gate signal timing to maintain proper synchronization, thereby resolving the asynchronous clock domain conflict
2Productivity
If the processor and memory operate in different clock domains to achieve higher reading/writing speeds, then productivity increases, but phase differences between clock signals cause harmful effects on data extraction accuracy
Solution Approach 1:
The data strobe gate signal generator acts as a mediator that receives inputs from both the processor clock domain and the memory data strobe signal, processes their phase relationship, and outputs a synchronized gate signal that eliminates phase difference interference while maintaining high-speed operation
Solution Approach 2:
The patent dynamically changes the timing parameters of the gate signal generated by the data strobe gate signal generator based on the detected phase relationship between clock domains, adjusting the gate signal's phase and duration to compensate for frequency and phase variations, thereby eliminating harmful phase difference effects
Data Source
AI summary
A processor circuit sends a read request. A clock signal of the processor circuit corresponds to a first counting value. A memory circuit stores data and sends a data strobe signal in response to the read request. The data strobe signal corresponds to a second counting value. The processor circuit includes a selector circuit and a feedback circuit. The selector circuit selects and outputs a flag signal from a plurality of flag control signals according to the second counting value. The feedback circuit generates an enable signal according to a set signal associated with the first counting value, the flag signal associated with the second counting value, and a data strobe gate signal, and generates the data strobe gate signal according to the enable signal and the data strobe signal. The processor circuit reads the data according to the data strobe gate signal.