Data Switch Buffer Management for Independent Spread Spectrum Clocks
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Solution Overview
Problem
Current data switches are unable to effectively process traffic from multiple sources with independently modulated spread-spectrum clocks (SSCs) without introducing excessive latency, as they require the same SSC signal to operate efficiently, and existing elastic buffer strategies are impractical for accommodating the broader frequency spectrum of SSCs.
Innovation Solution
A data switch design that operates with individual and unrelated SSC domains, featuring a receive buffer configured to detect packet boundaries and delay core-side read operations, ensuring that the receive buffer is not filled faster than it can be emptied, and utilizing a core clock that is not SSC-enabled but set at a frequency higher than the link clock to prevent overruns and underruns, with a link layer and timer to manage packet alignment and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If elastic buffer strategies are used to accommodate clock frequency differences, then data rate matching is improved, but latency increases significantly and buffer size requirements become impractical for SSC
Solution Approach 1:
The patent changes the fundamental parameter of clock frequency relationship by allowing independent SSC modulations on each link rather than requiring matched SSC signals. This enables the switch to handle frequency variations up to ±5600 ppm without requiring excessively large elastic buffers, thereby reducing latency while maintaining data rate matching reliability.
Solution Approach 2:
The patent implements dynamic watermark-based buffer management that adapts to varying SSC modulation conditions. The buffer watermarks are dynamically adjusted based on the actual frequency differences between source and destination, allowing the system to maintain reliable data transfer with minimal buffer size and thus minimal latency.
2Productivity
If switches require the same SSC signal from all sources, then processing efficiency is improved, but adaptability to multiple independent SSC sources deteriorates
Solution Approach 1:
The patent makes the switch universal by enabling it to handle both matched SSC signals and completely independent SSC modulations on different links simultaneously. The watermark mechanism provides a universal solution that works regardless of whether sources share the same SSC signal or have independent modulations, thus maintaining processing efficiency while dramatically improving adaptability.
Solution Approach 2:
The patent segments the clock domain synchronization problem by allowing each link to operate with its own independent SSC modulation characteristics. Instead of requiring global SSC synchronization across all sources, each link is independently managed with its own watermark thresholds, enabling the switch to process multiple independent SSC sources efficiently.
3Reliability
If larger elastic buffers are provided to accommodate maximum frequency differences, then data integrity is improved, but device complexity and buffer size requirements become impractical
Solution Approach 1:
The patent applies partial action by using just enough buffer capacity to handle the actual frequency variations encountered, rather than provisioning for maximum theoretical differences. The watermark mechanism triggers buffer management actions only when necessary, allowing the system to maintain data integrity with practical, manageable buffer sizes instead of requiring excessively large buffers.
4Reliability
If redundant data is added or discarded to balance data rates, then clock frequency differences are compensated, but link efficiency deteriorates
Solution Approach 1:
The patent enables the elastic buffer to self-regulate data flow based on watermark levels without requiring active insertion or deletion of redundant data. The buffer automatically absorbs frequency variations by adjusting its fill level between watermarks, allowing the system to compensate for clock frequency differences while maintaining link efficiency through natural buffer accumulation and depletion rather than active data manipulation.
Data Source
AI summary
A data switch for an integrated circuit comprising at least one link for receiving input data packets from an independently modulated spread spectrum clock (SSC) enabled source having predetermined spread spectrum link clock frequency characteristics, and at least one output for transmitting the data packets after passage through the switch, the switch further comprising at least one receive buffer having a link side and a core side for receiving the SSC modulated input data packets from the link, at least one transmit buffer and a core clock, wherein the core clock operates at a given frequency between predetermined error limits determined by oscillation accuracy alone and is not SSC-enabled, the core clock frequency being set at a level at least as high as the highest link clock frequency such that the receive buffer cannot be filled faster from its link side than it can be emptied from its core side.