Data Synchronization via Direct Completion Notification
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Solution Overview
Problem
Distributed computing systems face performance degradation due to internal latencies, particularly in data synchronization operations, which can lead to incomplete or stale data being used during computation, resulting in data coherency issues and increased overall computation time.
Innovation Solution
A data synchronization method that involves the network adapter transmitting a completion queue element directly to the hardware data processor, allowing it to perform a flush operation and ensure all data is written to memory before initiating computation, reducing the need for multiple message exchanges and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional multi-message exchange protocol is used for data synchronization, then data coherency can be ensured, but synchronization latency increases and performance deteriorates
Solution Approach 1:
The patent extracts the essential synchronization function from the complex multi-message protocol, implementing a simplified direct notification mechanism where the network adapter directly notifies the hardware data processor when data transfer is complete, eliminating unnecessary intermediate messages while maintaining data coherency
Solution Approach 2:
The patent introduces a synchronization buffer as an intermediary structure between the network adapter and hardware data processor, allowing the network adapter to write completion status without requiring immediate acknowledgment, thus reducing synchronization latency while ensuring data coherency
2Reliability
If multiple message exchanges are performed for data synchronization, then data coherency can be maintained, but device complexity and operation difficulty increase
Solution Approach 1:
The patent extracts only the essential synchronization signaling function from the complex protocol suite, implementing a streamlined mechanism that uses direct completion notifications and buffer-based coordination, significantly reducing protocol complexity while maintaining data coherency
Solution Approach 2:
The hardware data processor autonomously monitors the synchronization buffer and initiates computation operations when data completion is detected, eliminating the need for complex coordinated control messages between components
3Reliability
If data synchronization is performed before computation, then data coherency is ensured, but computation time increases due to waiting for synchronization
Solution Approach 1:
The patent implements preliminary data transfer in advance, with the network adapter continuously filling the synchronization buffer before the hardware data processor needs the data, so that when computation is initiated, data is already ready and no waiting occurs
Solution Approach 2:
The patent ensures continuous data flow by having the network adapter continuously transfer data to the synchronization buffer in parallel with other system operations, eliminating idle waiting time and maintaining continuous computation throughput while ensuring data coherency
Data Source
AI summary
In one example, a method comprises: receiving, by a hardware data processor and from a network adapter, a transfer complete message indicating that the network adapter has initiated a transfer of data received from a network to the hardware data processor, the transfer being performed over an interconnect coupled between the hardware data processor and the network adapter; based on receiving the transfer complete message, performing, by the hardware data processor, a flush operation to fetch any remaining portion of the data buffered in the interconnect to a local memory of the hardware data processor; based on determining that flush operation is complete, storing, by the data hardware processor, the transfer complete message at the local memory; and based on determining that the transfer complete message is stored at the local memory, starting the computation operation of the data at the hardware data processor or preforming an error handling operation.