Data Synchronizer for Lockstep Processor Signal Integrity
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Solution Overview
Problem
Lockstep processing systems face challenges in maintaining synchronization due to asynchronous inputs, which can lead to hardware failure detection issues and inconsistent operation, particularly when input signals change during sampling times.
Innovation Solution
A data synchronizer with cross-channel interfaces and compare logic is used to receive and compare signals between processing lanes, ensuring that signals are transmitted synchronously to maintain lockstep operation between processors, thereby preventing false hardware fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous inputs are provided to the lockstep processing system, then the system can operate with independent processors, but the processors may fail to remain synchronized when input signals change during sampling times
Solution Approach 1:
A data synchronizer is introduced as an intermediary component between asynchronous input devices and the lockstep processors. The synchronizer receives data from multiple devices, compares the data using compare logic, and only transmits matching data to both processors simultaneously. This mediator ensures that processors receive synchronized inputs even when source devices operate asynchronously, resolving the contradiction between independent operation and synchronization reliability.
2Reliability
If redundant processors are used for lockstep processing, then hardware failure detection capability is improved, but false hardware fault detection occurs when processors receive different inputs
Solution Approach 1:
The data synchronizer performs preliminary comparison of input data from multiple devices before transmitting to processors. By comparing data in advance and only transmitting matching data, the system prevents the condition that would lead to false fault detection. The processors receive guaranteed matching inputs, so any detected mismatch truly indicates a hardware failure rather than input desynchronization.
3Reliability
If signal comparison is performed for each input signal, then processor synchronization is maintained, but the system complexity increases due to additional comparison operations
Solution Approach 1:
The comparison function is segmented and distributed across multiple data synchronizer components, each handling specific input signals or device pairs. Rather than one complex centralized comparator, the system uses multiple specialized synchronizer instances that independently compare and synchronize their respective data streams. This segmentation reduces the complexity of individual comparison units while maintaining overall synchronization reliability.
Data Source
AI summary
A method for managing communications involving a lockstep processing comprising at least a first processor and a second processor can include receiving, at a data synchronizer, a first signal from a first device. The method can also include receiving, at the data synchronizer, a second signal from a second device. In addition, the method can include determining, by the data synchronizer, whether the first signal is equal to the second signal. When the first signal is equal to the second signal, the method can include transmitting, by the data synchronizer, the first signal to the first processor and the second signal to the second processor. Specifically, in example embodiments, transmitting the first signal to the first processor can occur synchronously with transmitting the second signal to the second processor.