Data Transfer Arbitration for Memory Bank Access Concentration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory interleave systems face performance drops due to delayed access requests concentrated on specific banks, leading to inefficient memory access in high-definition image processing applications.
Innovation Solution
A data transfer arbitration apparatus that selects data transfer requesting entities either randomly or based on priority, ensuring equal service chances and consecutive transfers across multiple memory banks to distribute access and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory interleave system is used to reduce delay time, then memory access speed is improved, but access requests may concentrate on specific banks causing performance drop
Solution Approach 1:
The patent applies dynamic arbitration by allowing the number of consecutive transfers to a same bank to vary based on real-time access patterns. The arbitration apparatus dynamically adjusts transfer sequences to prevent concentration on specific banks while maintaining high access speed through interleaving.
Solution Approach 2:
The patent changes the parameter of consecutive transfer count to a same bank from fixed to variable. By allowing this parameter to change based on access patterns, the system optimizes both access speed and prevents bank concentration issues.
2Device complexity
If fixed priority sequence is used for data transfer service, then control is simplified, but access concentration on specific banks occurs reducing overall performance
Solution Approach 1:
The patent transitions from fixed priority control to dynamic arbitration where the number of consecutive transfers is variable. This dynamic approach maintains relatively simple control while preventing access concentration and improving overall processing performance.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
When a concentration of access requests on a specific bank occurs, the delay time is caused due to the competition among the accesses, thereby lowering the processing speed of an information processing apparatus as a whole. A data transfer arbitration unit 172 sequentially transfers data to be recorded to a memory controller 160 that records data in memory having a plurality of banks. A selector 174 selects any DMAC 170 from among a plurality of DMACs, irrespective of priority sequence of transfer service for the DMAC. A transmitter 176 transmits, to a control-side transfer unit 114, data requested to be transferred by the selected DMAC 170. The selector 174 selects consecutively the DMAC 170 so that the transfer service for the same DMAC is consecutively executed, and determines the number of consecutive selections so that a transfer across the banks of the DMAC 170 occurs by a plurality of the transfer services.