Data Transfer Circuit Clock Synchronization
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Solution Overview
Problem
Existing data transfer circuits face challenges in speeding up clock synchronization due to gradual frequency division number control and inability to effectively handle variations caused by disturbances.
Innovation Solution
A data transfer circuit that includes a memory, a clock generation circuit capable of multiplying a reference clock by a rational number, a frequency error estimation circuit to estimate the frequency error between clocks, and an adjustment circuit to output an adjustment multiple, allowing for immediate adjustment of the frequency division number to synchronize clocks quickly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the frequency division number is controlled gradually based on pointer difference comparison, then the synchronization stability is improved, but the clock synchronization time becomes excessively long
Solution Approach 1:
The patent performs preliminary frequency error estimation using the pointer difference change amount before actual frequency adjustment. This preliminary action allows the system to predict the required frequency correction in advance, enabling direct setting of the frequency division number to the target value rather than gradual adjustment, thus significantly reducing synchronization time while maintaining stability
Solution Approach 2:
The patent replaces the mechanical gradual adjustment mechanism with a computational approach. By substituting the physical trial-and-error frequency adjustment with mathematical estimation based on pointer difference analysis, the system can calculate the optimal frequency division number directly and apply it immediately, eliminating the time-consuming gradual adjustment process
2Measurement precision
If the frequency division number is adjusted based on pointer difference, then the frequency alignment is improved, but the accuracy deteriorates due to disturbance and temporal frequency variations
Solution Approach 1:
The patent extracts only the relevant portion of pointer difference data that reflects actual frequency error, separating it from noise caused by disturbances and temporal variations. By focusing on the meaningful change amount rather than raw pointer differences, the system achieves accurate frequency estimation despite environmental干扰
Solution Approach 2:
The patent implements feedback by continuously monitoring the pointer difference change amount and using it to correct frequency division number adjustments. This closed-loop feedback mechanism allows the system to adapt to frequency variations while filtering out transient disturbances, maintaining both accuracy and reliability
Data Source
AI summary
A data transfer circuit according to the invention includes a memory configured to write data in accordance with a write pointer in synchronization with a first clock, and read out the data in accordance with a readout pointer in synchronization with a second clock, a clock generation circuit configured to generate the second clock by multiplying a reference clock by a rational number N, a frequency error estimation circuit configured to estimate a frequency error between the first clock and the second clock based on a change amount of a pointer difference between the write pointer and the readout pointer, and an adjustment circuit configured to output, as an adjustment multiple ΔN, a value obtained by dividing the estimated frequency error by a frequency of the reference clock. The clock generation circuit generates the second clock by multiplying the reference clock by a rational number (N+ΔN).