Data Transfer Controller for Semiconductor Apparatus
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Solution Overview
Problem
As microcomputer functions and controlled units increase, existing data transfer techniques in single-chip microcomputers face challenges in accuracy and efficiency, leading to increased physical size and processing time due to the need for dedicated hardware for each type of input data.
Innovation Solution
A semiconductor apparatus with a data transfer controller that performs calculations on source address information and writes data based on destination address information, allowing for efficient data transfer and output generation by referring to table data, thereby minimizing hardware requirements and simplifying configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated hardware is provided for every type of input data to improve control accuracy, then control accuracy is improved, but physical size and device complexity increase
Solution Approach 1:
The data transfer controller is designed as a universal hardware unit that can handle multiple types of data transfer operations (byte transfer, word transfer, block transfer, repeat transfer) through a single integrated structure. The controller uses mode specification bits and configurable address registers to adapt to different transfer requirements, eliminating the need for separate dedicated hardware for each transfer type while maintaining control accuracy.
Solution Approach 2:
The data transfer controller implements dynamic configurability through mode specification registers and address registers that can be programmed at runtime. The controller can switch between different transfer modes (normal, block, repeat) and adjust source/destination addresses dynamically, allowing a single hardware unit to perform functions that would otherwise require multiple static hardware components.
2Reliability
If dedicated hardware is provided for every type of input data to improve control accuracy, then control accuracy is improved, but processing time increases
Solution Approach 1:
By providing a single universal data transfer controller that can handle all transfer types, the system avoids the time penalty of switching between multiple dedicated hardware units. The controller maintains internal state and configuration between operations, enabling seamless transition between different transfer modes without requiring reinitialization of separate hardware components.
Solution Approach 2:
The controller pre-configures transfer parameters including source address, destination address, transfer count, and mode specification in registers before execution. This preliminary setup allows the actual data transfer to proceed efficiently without runtime decision-making delays, as all control parameters are predetermined and loaded into the controller's register file.
3Device complexity
If a data transfer controller is provided to perform data transfer by small amount of hardware, then hardware size is reduced, but the content of data transfer is not taken into account limiting applicability
Solution Approach 1:
The data transfer controller employs parameter specification through mode bits and register values to adapt its behavior. By changing parameters such as transfer size (byte/word), transfer mode (normal/block/repeat), and address registers, the same hardware structure can perform diverse data transfer operations. This parameter-based configuration allows the controller to handle different data contents and transfer scenarios without requiring structural modifications.
Solution Approach 2:
The controller architecture segments the data transfer function into independent configurable components: mode specification bits, source address registers, destination address registers, and transfer count registers. This segmentation allows each component to be independently configured for different transfer scenarios, enhancing versatility while maintaining a compact overall structure.
4Productivity
If data transfer information is held in dedicated hardware to enable short address mode or full address mode, then hardware efficiency is improved, but one of the source address or destination address will be at RAM requiring coordination during updates
Solution Approach 1:
The data transfer controller merges the address holding function and transfer control function into a single integrated unit. Both source and destination addresses are held within the controller's internal register file, eliminating the need for external RAM access during address updates. This integration allows simultaneous modification of address registers without coordination overhead, as all registers are internally managed by the controller.
Data Source
AI summary
An object is to obtain output data corresponding to input data by referring to table data by a semiconductor apparatus having a simple configuration. An MCU includes a DTC for transferring data from a source address region to a destination address region based on data transfer information in response to a startup request. The DTC performs an operation on second source address information based on data that has been read from first source address information, performs reading based on a result of the operation, and writes read data based on destination address information.