Data Transfer Device Offloads Host CPU Processing Load
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Solution Overview
Problem
As network and storage device performance improve, the processing loads on host CPUs increase significantly due to software processing interposed in data transfer between storage devices and network interfaces, leading to high memory loads and increased costs and power consumption when upgrading CPUs to handle high-speed data transfer rates.
Innovation Solution
A data transfer device with a communication processor, receiving buffer, and command issuance controller that receives file data from a network and writes it to a storage device based on map information, offloading the data transfer processing from the host CPU and reducing memory loads by performing data transfer operations in hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software processing is used for data transfer between storage device and network interface, then data transfer can be performed with general-purpose host CPU, but processing load on host CPU and memory load increase significantly
Solution Approach 1:
The patent extracts the data transfer processing function from the host CPU by introducing a dedicated data transfer device. This device includes a reception buffer for storing received data, a transmission buffer for holding data to be transmitted, and a control unit that manages data transfer between storage devices and network interfaces independently of the host CPU, thereby reducing the host CPU's processing load while maintaining system versatility
Solution Approach 2:
The patent introduces a dedicated data transfer device as an intermediary between the host CPU and the data transfer operations. This intermediary handles all data reception from network interfaces, storage in reception buffers, data retrieval from storage devices, and transmission to network interfaces, allowing the host CPU to focus on higher-level tasks while the intermediary manages the cumbersome data transfer processing
2Speed
If high-performance host CPU is used to handle high-speed data transfer, then data transfer rate can be improved, but costs and power consumption increase
Solution Approach 1:
The patent extracts the high-speed data transfer processing from the host CPU by implementing a dedicated data transfer device with specialized buffers and control logic. This device handles data reception, buffering, and transmission independently, enabling high-speed data transfer rates without requiring the host CPU to operate at high performance levels, thus reducing power consumption and cost
Solution Approach 2:
The dedicated data transfer device performs self-service by autonomously managing data reception from network interfaces, storing data in reception buffers, retrieving data from storage devices, and transmitting data to network interfaces without requiring continuous intervention from the host CPU. This self-service capability enables sustained high-speed data transfer while keeping the host CPU in a low-power state
3Device complexity
If data is transferred through main memory with software processing, then data transfer can be performed using conventional architecture, but memory load increases greatly
Solution Approach 1:
The patent extracts data transfer operations from the main memory path by introducing a dedicated data transfer device with its own reception and transmission buffers. Data is transferred directly between storage devices and network interfaces through these dedicated buffers, bypassing the main memory and eliminating the need for software-mediated data copying, thus greatly reducing memory load while maintaining architectural simplicity
Solution Approach 2:
The dedicated data transfer device acts as an intermediary that eliminates the need for main memory as a data transfer medium. The device includes reception buffers for incoming data and transmission buffers for outgoing data, allowing direct data transfer between storage devices and network interfaces without routing through main memory, thereby reducing memory load while preserving conventional system architecture
Data Source
AI summary
The data transfer device receives file data through a network and writes the file data to a storage device on a block basis, in which the communication processor receives a receiving instruction for the file data from an external host CPU and receives the file data via one or more packets from the network according to the receiving instruction, the receiving buffer stores data received in the communication processor therein upon receiving each packet, and the command issuance controller acquires, from the external host CPU, map information indicating a position to write the file data in a storage area of the storage device, specifies data in the receiving buffer for writing according to a data storing status of the receiving buffer, issues a write command for writing a specified data to the storage device and sends it to the storage device.