Data Transfer Device with Interrupt Controller for DMA Management

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Solution Overview

Problem

In data transfer systems, the processor is burdened with excessive processing load and bus occupancy due to the need for frequent read operations to manage multiple DMA circuits, leading to inefficiencies in data transfer operations.

Innovation Solution

A data transfer device comprising multiple transfer circuits managed by a processor, with a request accepting unit, a status information collecting unit, and a notification data generating unit that reduces processor load by generating and transmitting notification data containing transfer request information and status updates, allowing for speedy data transfer without processor intervention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the processor frequently reads status information from multiple DMA circuits to manage data transfer, then the reliability of data transfer management is improved, but the processor load and bus occupancy increase significantly

Engineering Contradiction:

Improvedata transfer management reliabilityVSAvoiddata transfer efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

An interrupt controller is introduced as an intermediary between the DMA circuits and the processor. The interrupt controller collects status information from multiple DMA circuits and manages interrupt requests, thereby reducing the processor's direct involvement in status monitoring and minimizing bus occupancy while maintaining reliable data transfer management.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The DMA circuits are designed to autonomously generate interrupt requests when data transfer is complete, without requiring the processor to continuously query their status. This self-service mechanism allows the processor to focus on higher-level tasks while the DMA circuits independently notify the system of their completion status.

Inventive Principle:

Principle #25Self-service

2Measurement precision

If the CPU interrupts data transfer processing to read transfer status information from DMA circuits, then the accuracy of transfer status monitoring is improved, but the data transfer speed decreases due to processing interruptions

Engineering Contradiction:

Improvetransfer status monitoring accuracyVSAvoiddata transfer speed

Core Design Contradiction:

Measurement precisionVSSpeed

Solution Approach 1:

An interrupt feedback mechanism is implemented where DMA circuits automatically send completion status to the processor via interrupt signals. This allows the processor to obtain accurate transfer status information without continuously polling the DMA circuits, thereby maintaining monitoring accuracy while avoiding interruptions to the data transfer process.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The system is configured to prepare and send interrupt requests in advance when data transfer is complete, so the processor receives notification exactly when needed without having to wait or interrupt ongoing processing. This preliminary action ensures accurate status monitoring is achieved without impacting transfer speed.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If multiple DMA circuits operate in parallel to increase data transfer capacity, then the productivity of data transfer is improved, but the complexity of processor management increases

Engineering Contradiction:

Improvedata transfer capacityVSAvoidprocessor management complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The management function is segmented between the processor and the interrupt controller. The processor handles high-level data transfer coordination while the interrupt controller manages the detailed status collection and interrupt request generation from multiple DMA circuits. This segmentation reduces the processor's management burden while maintaining parallel data transfer capacity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The interrupt controller serves as a universal management interface for multiple DMA circuits, handling status collection, interrupt request generation, and prioritization for all DMA circuits through a single unified mechanism. This multi-functional approach simplifies processor management complexity while supporting multiple parallel DMA operations.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS7757016B2Data transfer device, semiconductor integrated circuit, and processing status notification method

Publication Date: 2010.07.13 FUJITSU LTD

AI summary

According to an aspect of an embodiment, a data transfer device comprises a plurality of transfer circuits managed by a processor, a request accepting unit, a status information collecting unit and a notification data generating unit. The plurality of transfer circuits each controls transfer of data. The request accepting unit accepts a transfer request from at least one of the plurality of transfer circuits. The status information collecting unit collects status information indicating status of data transfer relating to all of the plurality of transfer circuits, upon acceptance of the transfer request. The notification data generating unit generates notification data including information of the transfer circuit regarding which the request accepting unit has received the transfer request and status information collected by the status information collecting unit. And the notification data generating unit transmits the generated notification data to the processor.