Data Transmission Circuit Using Bus Inversion Encoding

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Solution Overview

Problem

High-speed data transmission in semiconductor systems faces challenges due to decreased signal amplitudes, making precise data communication difficult, as increased data transmission speed and low power consumption require maintaining voltage levels on signal transmission lines.

Innovation Solution

A data transmission circuit that employs data bus inversion encoding and decoding to compare previous and current output data, inverting or non-inverting data to maximize data transitions and maintain signal line voltage levels, thereby facilitating efficient data communication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data transmission speed is increased, then productivity is improved, but signal amplitude decreases making precise data communication difficult

Engineering Contradiction:
Improvedata transmission speedVSAvoiddata communication precision
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent implements a data bus inversion encoding circuit that monitors previous output data and current output data, using this feedback information to dynamically control inversion of data bits. This feedback mechanism ensures optimal signal transitions are achieved, maintaining signal integrity and communication precision even at high transmission speeds where amplitude degradation occurs.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent dynamically changes the inversion parameter of data bits based on comparison between previous and current output data. By conditionally inverting data bits when transitions are detected, the system adapts signal characteristics to maintain valid window duration and communication precision despite increased transmission speed and reduced signal amplitude.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If data transmission speed is increased, then productivity is improved, but the valid window and duration of data decreases

Engineering Contradiction:
Improvedata transmission speedVSAvoidvalid window duration
Core Design Contradiction:
ProductivityVSDuration of action of moving object

Solution Approach 1:

The patent performs preliminary inversion encoding of data bits before transmission by comparing previous output data with current output data. This preliminary action ensures that data transitions are optimized in advance, creating sufficient valid window duration for reliable reception even when operating at high transmission speeds where the natural valid window would be too short.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If data bus inversion encoding is implemented to maximize data transitions, then communication precision is improved, but device complexity increases

Engineering Contradiction:
Improvecommunication precisionVSAvoidencoding circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the data bus into individual bit positions and processes each bit independently through comparison with previous output data. This segmentation approach allows the inversion encoding to be implemented through simple parallel comparisons rather than complex sequential logic, reducing overall device complexity while maintaining communication precision.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10942883B2Data transmission circuit for operating a data bus inversion, and a semiconductor apparatus and a semiconductor system including the same
Publication Date: 2021.03.09 SK HYNIX INC
  • US10942883B2 patent drawing
  • US10942883B2 patent drawing
  • US10942883B2 patent drawing

AI summary

A data transmission circuit includes a data bus inversion encoding circuit configured to compare previous output data and current output data, invert or non-invert the current output data to control the number of data transitions; and transmitters configured to drive signal transmission lines based on outputs of the data bus inversion encoding circuit.