Data Transmission Circuit Delay Module Timing Control
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Solution Overview
Problem
Designing data transmission circuits for specific types of semiconductor storage devices poses a challenge in setting the response mode register read command to read out setting parameters while matching the timing with array area data read commands, necessitating a shared data transmission channel without increasing circuit occupancy area.
Innovation Solution
Incorporating a delay module that generates a delayed read command after a preset time from receiving the mode register read command, allowing the mode register data processing unit to read and output setting parameters, thereby matching the response time with array area data read commands and sharing a data transmission channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the mode register read command uses a separate data transmission channel, then the setting parameters can be read out independently, but the circuit occupancy area increases
Solution Approach 1:
The patent combines the mode register read command transmission path with the array area data read command transmission path, allowing both types of commands to share the same data transmission channel. This merging eliminates the need for a separate transmission channel for mode register reads, thereby reducing circuit occupancy area while maintaining independent reading capability through timing control mechanisms.
Solution Approach 2:
The data transmission channel is designed to serve multiple functions: it can transmit both mode register read commands and array area data read commands. By making the transmission channel universal, the patent avoids the need for dedicated channels for different command types, thus reducing overall circuit area while preserving the ability to read setting parameters independently when needed.
2Area of stationary object
If the mode register read command shares the data transmission channel with array area data read command, then the circuit occupancy area is reduced, but the timing coordination becomes complex
Solution Approach 1:
The patent employs a delay module that introduces a preset time delay to the mode register read command before it is transmitted through the shared data transmission channel. This preliminary timing adjustment ensures that the delayed command is transmitted at an appropriate moment, avoiding conflicts with array area data read commands and simplifying the overall timing coordination by proactively managing potential timing conflicts.
Solution Approach 2:
The delay module acts as an intermediary component between the command input and the shared transmission channel. It mediates the timing of mode register read commands, introducing a controlled delay that facilitates smooth sharing of the transmission channel with array area data read commands, thereby reducing timing control complexity.
3Area of stationary object
If the response time of mode register read command is adjusted to match array area data read command, then the shared channel can be used, but the working parameter requirements may not be met
Solution Approach 1:
The patent introduces a delay module that dynamically adjusts the timing of mode register read commands by adding a preset time delay. This dynamic timing adjustment allows the system to meet the working parameter requirements for reading setting parameters while also enabling the command to share the data transmission channel with array area data read commands, thus reducing circuit occupancy area without compromising reliability.
Data Source
AI summary
This application relates to a data transmission circuit, a method, and a storage device. The data transmission circuit includes a delay module and a mode register data processing unit. The delay module delays a first preset time when receiving a mode register read command, and generates delayed read command. The mode register data processing unit is connected to the delay module, and reads setting parameters from the mode register in response to the mode register read command, and outputs the setting parameters in response to the delayed read command.