Data Transmission Circuit Wiring Complexity Reduction
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Solution Overview
Problem
Conventional semiconductor memory apparatuses face issues with high energy consumption and complex wiring due to the large number of signal transmission wires between the mode register read-write module and the internal cache module, leading to inter-symbol interference during data transmission.
Innovation Solution
A circuit and method incorporating multiple mode register decoding modules, mode register read-write modules, and a logic gate module to generate and process signals, reducing the number of signal transmission wires by sharing data transmission paths and calculating OR values of output data, thereby decreasing energy consumption and wiring complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transmitted in parallel via multiple signal transmission wires between mode register read-write modules and internal cache module, then data transmission accuracy is improved by avoiding inter-symbol interference, but the number of signal transmission wires increases, leading to complex wiring and increased energy consumption
Solution Approach 1:
The patent merges multiple parallel data transmission channels into a single shared transmission wire by using time-division multiplexing. Different mode register read-write modules transmit data sequentially on the same wire, eliminating the need for multiple parallel wires while maintaining data transmission accuracy through proper timing control and data validation mechanisms.
Solution Approach 2:
The patent implements periodic action by assigning specific time slots to different mode register read-write modules for data transmission. Each module transmits data at predetermined intervals according to a cyclic schedule, allowing multiple modules to share a single transmission wire without interference while reducing wiring complexity.
2Productivity
If multiple parallel signal transmission wires are used between mode register read-write modules and internal cache module, then data transmission speed is improved, but energy consumption increases due to the large number of wires
Solution Approach 1:
The patent combines multiple high-speed parallel transmission channels into a single time-division multiplexed channel. By allowing different modules to transmit data sequentially at high speeds during their allocated time slots, the system achieves aggregate data transmission capacity equivalent to multiple parallel wires while consuming less energy due to the reduced number of physical transmission lines.
3Device complexity
If the number of signal transmission wires is reduced, then wiring complexity and energy consumption are decreased, but data transmission efficiency may be affected
Solution Approach 1:
The patent uses periodic time-division multiplexing to maintain high data transmission efficiency with reduced wiring. Each mode register read-write module is assigned regular time slots for data transmission, ensuring continuous and efficient data flow while sharing a single transmission wire, thus maintaining productivity while reducing device complexity.
Data Source
AI summary
A circuit and method for data transmission, and a storage apparatus are provided. A mode register decoding module is configured to generate a mode register unselected enable signal, a mode register read enable signal, or a mode register write enable signal according to received mode register address information, a mode register read control signal, or a mode register write control signal. A mode register read-write module is configured to: cache data on data line according to mode register write enable signal in write state, and output selected data and unselected data after setting the unselected data to zero according to the mode register read enable signal and the mode register unselected enable signal in a read state. The logic gate module is configured to calculate an OR value of the data outputted by each mode register read-write module in the read state and output a calculation result.