Data Transmission Memory Device for Processor Coprocessor Communication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In computer systems, the data transmission between a standard processor and a coprocessor is inefficient due to the need to transfer all instruction parameters, even if they remain unchanged, leading to increased clock cycles and reduced processing performance, especially in loose coupling scenarios where high memory requirements and asynchronous data processing cause delays.
Innovation Solution
A data transmission memory device with two memory regions allows for overlapping data transfer and execution by enabling the standard processor to write new instruction parameters while the coprocessor executes previous instructions, and only transmitting changed parameters, thereby reducing the need for complete data record transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all instruction parameters are transferred from standard processor to coprocessor, then the coprocessor has complete information for execution, but the data transmission time and clock cycles increase
Solution Approach 1:
The patent extracts only the changed parameters from the complete instruction parameter set and transfers only these to the coprocessor, rather than transferring all parameters. This is achieved by comparing the current parameter set with the previously transferred set and identifying only the differences that need to be updated.
Solution Approach 2:
The patent applies partial action by transferring only the necessary subset of parameters (those that have changed) rather than the complete set. This partial transfer is sufficient for coprocessor execution while significantly reducing transmission overhead.
2Measurement precision
If complete data records are transferred to coprocessor, then execution accuracy is maintained, but memory bandwidth and transmission efficiency decrease
Solution Approach 1:
The patent extracts and transfers only the changed parameters rather than complete data records, maintaining execution accuracy by ensuring all necessary updated information is transmitted while reducing unnecessary data transfer.
3Stability of the object's composition
If standard processor waits for coprocessor execution to complete before transferring next parameters, then data synchronization is maintained, but processing throughput decreases
Solution Approach 1:
The patent enables the standard processor to prepare and transfer the next set of instruction parameters while the coprocessor is still executing previous instructions. This preliminary action maintains synchronization because the parameter transfer is based on change detection rather than execution completion status.
Solution Approach 2:
The patent ensures continuous useful action by allowing the standard processor to continuously prepare and transfer parameters without idle waiting periods, while the coprocessor continuously executes instructions. The asynchronous operation with change-based transfer maintains system coherence.
4Speed
If coprocessor is specialized for specific tasks, then execution speed for those tasks increases, but flexibility to execute general programs decreases
Solution Approach 1:
The patent enables the specialized coprocessor to handle multiple different instruction types and tasks by receiving dynamically updated parameter sets that specify different operations. The parameter-based control mechanism provides universality while the specialized hardware provides speed.
Data Source
AI summary
One aspect relates to a computer system including a first data processing unit, a second data processing unit and a data transmission/memory device. The data transmission/memory can transmit sets of data from the first data processing unit to the second data processing unit. The data transmission/memory device includes a first memory region and a second memory region.