Asynchronous Data Transmission Memory Segmentation

The shared memory is segmented into three separate data transmission memories (DTM0, DTM1, DTM2), each dedicated to specific transmission cycles. This segmentation allows the transmitter to write to one DTM while the receiver reads from another, eliminating mutual blocking and collision risks while maintaining high data transmission speed.

Control memory bits (CM0, CM1, CM2) are introduced as intermediaries to manage access rights to each DTM. These control bits act as mediators that coordinate between transmitter and receiver, preventing collisions by granting exclusive access rights without requiring both modules to have simultaneous read-write access to the same memory location.

Different access rights are assigned to different memory locations based on local requirements. The transmitter has write access to DTMs during its write phase, while the receiver has read access to DTMs during its read phase. This localized access control maintains communication flexibility while preventing mutual blocking, as each module operates on different memory regions at different times.

The system uses periodic action through cyclic bit setting and resetting in control memories. The transmitter periodically sets write access bits, performs writes, then clears them. The receiver periodically sets read access bits, performs reads, then clears them. This periodic access pattern ensures continuous data transmission without mutual blocking, as access rights are systematically rotated between modules.