Data-Width-Aware Memory ECC for Lower Storage Overhead
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Solution Overview
Problem
Existing memory systems face reliability issues due to increased storage capacity per unit area, necessitating additional storage space for error correction, which is inefficient and costly.
Innovation Solution
A memory system with a data-width aware (DWA) encoder and decoder that generates and processes code word groups based on data word sizes, performing error detection and correction in multiple modes to enhance reliability without additional storage space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional storage space is allocated for error correction codes, then reliability is improved, but storage capacity efficiency deteriorates
Solution Approach 1:
The patent changes the parameter of error correction capability by implementing multiple error correction modes (first mode with higher correction capability, second mode with lower correction capability). The system dynamically adjusts the error correction level based on data characteristics, allowing reliable operation without always using the maximum storage overhead required by fixed high-capability ECC schemes.
Solution Approach 2:
The patent introduces dynamic selection of error correction modes based on runtime conditions. The memory controller can switch between first and second error correction modes depending on the type of data being processed, enabling the system to optimize between reliability and storage efficiency in real-time rather than being constrained by a static high-overhead ECC configuration.
2Device complexity
If uniform error correction is applied to all data widths, then simplicity is maintained, but performance optimization deteriorates
Solution Approach 1:
The patent applies local quality by implementing data-width aware error correction that tailors the correction strategy to the specific data width being processed. Different error correction parameters and algorithms are applied to different data widths (e.g., 64-bit vs. 128-bit data), optimizing performance for each case rather than using a one-size-fits-all approach that would require excessive overhead for wider data paths.
Solution Approach 2:
The patent changes error correction parameters based on data width. The system selects different error correction codes, code rates, and correction capabilities according to the specific data width being processed. This allows the memory system to achieve optimal performance for each data width configuration without being constrained by a fixed, overly complex uniform error correction scheme.
Data Source
AI summary
A memory system includes a memory module and a memory controller. The memory module stores a code word group including first and second data words and a flag. The memory controller includes an error correction code (ECC) engine including a data-width aware (DWA) encoder that generates the code word group by using the first and second data words, and performs an error detection and error correction operation in one of first to third modes based on a size of each of the first and second data words, and a DWA decoder that receives the code word group, performs an error detection and error correction operation in one of the first to third modes according to a type of the code word group determined based on the flag, and extracts the first data word and the second data word from the code word group.