Data-Valid Window Tracking for High-Speed Interface Sampling
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Solution Overview
Problem
Efficiently maintaining high throughput communication through the interface between a memory controller and nonvolatile memory dies is challenging due to drift in Data-Valid Windows (DVWs), which can lead to misalignment and increased Bit Error Rates (BERs).
Innovation Solution
Implementing on-the-fly DVW tracking and adjustment using pointers to detect and correct misalignment by shifting sampling times without interrupting data transfer, utilizing control circuits connected to the data bus to track DVW drift and adjust sampling times accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DVW training methods are used to maintain alignment, then data accuracy is improved, but data transfer throughput is reduced due to interruptions
Solution Approach 1:
The patent implements continuous DVW tracking during active data transfer by comparing bits sampled at different times (first bit at time T1, second bit at time T2, third bit at time T3). This allows the system to detect and correct sampling misalignment without interrupting the data transfer stream, maintaining both accuracy and throughput.
Solution Approach 2:
The patent employs feedback mechanisms where sampled bits are compared to detect DVW drift direction (left or right shift), and sampling timing is adjusted accordingly. This closed-loop feedback enables real-time adaptation to changing DVW conditions during ongoing data transfer operations.
2Reliability
If frequent DVW retraining is performed to correct misalignment, then bit error rate is reduced, but power consumption increases
Solution Approach 1:
The patent performs preliminary DVW alignment during initial training or when conditions change significantly. Between these periodic training events, the system maintains alignment through lightweight continuous tracking using three sample points, avoiding the need for frequent full retraining operations that would consume excessive power.
Solution Approach 2:
Instead of performing full DVW retraining operations frequently, the patent uses a partial action approach by sampling only three specific bits at specific times to detect drift. This partial monitoring mechanism provides sufficient correction capability with minimal power consumption compared to complete retraining.
3Measurement precision
If sampling timing is adjusted to track DVW drift, then data alignment is improved, but system complexity increases
Solution Approach 1:
The patent segments the DVW tracking function into discrete, manageable components: three fixed sampling time points (T1, T2, T3), bit comparison logic to detect drift direction, and timing adjustment mechanisms. This segmentation simplifies the overall control circuit design while achieving precise sampling alignment.
Data Source
AI summary
An apparatus includes one or more control circuit configured to connect to a data bus. The one or more control circuit is configured to compare a first bit sampled on a first side of a Data Valid Window (DVW) of a data signal with a middle bit from the middle of the DVW and compare a second bit sampled on a second side of the DVW with the middle bit to detect misalignment of sampling with the DVW. The one or more control circuit is configured to adjust sampling times for the data signal according to detection of misalignment.