Data Writing Alignment and Compression Handling
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Solution Overview
Problem
The writing performance of data into storage is poor due to a high number of partial writing operations, where the bit width of the data is less than the bus bit width of the storage.
Innovation Solution
A data writing method that determines if the start storage address of a data block is aligned with the bus bit width, and if not, checks if the preceding data block is compressed, executing complete writing on the first beat of the data block when it is, thereby adjusting the writing from partial to complete and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If partial writing operations are used when data bit width is less than bus bit width, then data can be written into storage, but writing performance deteriorates due to excessive number of partial writing operations
Solution Approach 1:
The system performs preliminary actions by checking address alignment and compression status before executing write operations. The mask register is pre-configured with alignment bits set to 1, and the system determines in advance whether complete or partial writing should be performed, thereby optimizing the write operation sequence and improving overall writing performance
Solution Approach 2:
The system dynamically changes the writing mode parameter between complete writing and partial writing based on address alignment conditions. When the start address is aligned with bus bit width, complete writing is executed; when misaligned, partial writing with appropriate mask configuration is performed, thereby adapting to different scenarios and improving writing efficiency
2Productivity
If complete writing is executed on misaligned data blocks without checking compression status, then writing performance may improve, but writing errors occur due to data corruption from compressed blocks
Solution Approach 1:
The system implements feedback by checking the compression status of the previous data block before determining the write operation mode. The mask register is conditionally configured based on this feedback - set to all 1s when the previous block is compressed (enabling complete writing), and configured with alignment bits only when the previous block is not compressed (enabling partial writing), thereby ensuring both performance and accuracy
Solution Approach 2:
The system performs preliminary verification of compression status before executing write operations. By checking whether the previous data block is compressed in advance and configuring the mask register accordingly, the system prevents writing errors while maintaining optimal writing performance through appropriate selection of complete or partial writing modes
3Productivity
If address alignment is not checked, then the writing process is simpler, but partial writing operations increase reducing writing performance
Solution Approach 1:
The system performs preliminary address alignment checking and mask configuration before executing write operations. The mask register is pre-configured with alignment bits set to 1 based on address analysis, enabling the system to determine in advance whether complete or partial writing should be performed, thereby optimizing write operation efficiency without adding significant complexity
Solution Approach 2:
The system achieves self-service by automatically determining the appropriate write mode (complete or partial) based on address alignment conditions and compression status. The mask register is automatically configured with the correct bit pattern, and the system autonomously selects the optimal writing strategy without requiring external intervention, thereby improving performance while managing complexity internally
Data Source
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AI summary
The present application relates to the field of data reading and writing technologies, and discloses a data writing method and a data writing apparatus, and an electronic device. The data writing method comprises: determining whether a start storage address of a first data block is aligned with a bus bit width of a storage (902); in response to that the start storage address of the first data block is not aligned with the bus bit width of the storage, determining whether a second data block which is a data block immediately before the first data block is compressed,; in response to that the second data block is compressed, executing complete writing on a first beat of the first data block.