Database Offloading Engine for CPU Power Reduction
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Solution Overview
Problem
Table scan and sum aggregation operations in databases significantly burden the CPU, consuming a substantial fraction of CPU cycles and power, necessitating an improved system for efficient performance.
Innovation Solution
A database offloading engine with a vectorized adder, read-modify-write circuits, sum buffers, a key address table, and a control circuit that offloads these operations from the host CPU, utilizing NVDIMM-p or PCIe interfaces for connection, and includes table scanning circuits for condition testing and sum aggregation operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If table scan and sum aggregation operations are performed by host CPU, then database query processing can be executed, but CPU cycles and power consumption are significantly burdened
Solution Approach 1:
The patent extracts table scan and sum aggregation operations from the host CPU and implements them in dedicated hardware circuits within the storage device. The table scanning circuit and vectorized adder are separate hardware components that offload these specific functions from the general-purpose CPU, thereby reducing CPU power consumption while maintaining database query processing capability.
Solution Approach 2:
The patent introduces a database offloading engine as an intermediary component between the host CPU and the storage medium. This offloading engine includes specialized hardware circuits that handle table scan and aggregation operations, acting as a mediator that transfers these computationally intensive tasks from the CPU to dedicated hardware, thus reducing overall system power consumption.
2Productivity
If table scan and sum aggregation operations are performed by host CPU, then database query processing can be executed, but processing speed is reduced due to CPU burden
Solution Approach 1:
The patent replaces the software-based CPU execution model with hardware-based circuit execution for table scan and aggregation operations. The table scanning circuit and vectorized adder are hardware implementations that operate at circuit speeds rather than software instruction cycle speeds, significantly improving processing speed while maintaining the same database query processing functionality.
Solution Approach 2:
The patent segments the database processing system into distinct functional components: the host CPU for high-level query management, the table scanning circuit for efficient table scans, the vectorized adder for parallel aggregation, and the key-value store for data storage. This segmentation allows each component to operate in its optimal performance regime, with hardware circuits handling computationally intensive operations at high speed.
3Productivity
If dedicated hardware circuits are introduced for table scan and aggregation, then processing efficiency is improved, but device complexity increases
Solution Approach 1:
The patent merges the table scanning circuit, vectorized adder, key-value store, and control logic into a single integrated database offloading engine that resides within the storage device. This consolidation reduces overall system complexity by eliminating the need for separate hardware components and interconnections, while still providing specialized hardware acceleration for table scan and aggregation operations.
Data Source
AI summary
A database offloading engine. In some embodiments, the database offloading engine includes a vectorized adder including a plurality of read-modify-write circuits, a plurality of sum buffers respectively connected to the read-modify-write circuits, a key address table, and a control circuit. The control circuit may be configured to receive a first key and a corresponding first value; to search the key address table for the first key; and, in response to finding, in the key address table, an address corresponding to the first key, to route the address and the first value to a read-modify-write circuit, of the plurality of read-modify-write circuits, corresponding to the address.