Database SSD Architecture With Parallel ASIC Cores and High Parity
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Solution Overview
Problem
Existing data storage devices lack the necessary data throughput and processing capability to efficiently perform database operations, such as select, update, and delete, due to their limited capabilities compared to host systems.
Innovation Solution
The implementation of a front-end ASIC with 256 to 512 RISC processing cores that decomposes and parallelizes host commands to front-end module ASICs, each coupled to multiple NVM dies, increasing parity bits to 33.3% for reduced bit error rate and enhanced data throughput, enabling the processing of database operations within the SSD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional data storage device architecture is used, then device complexity is low, but data throughput and processing capability are insufficient for database operations
Solution Approach 1:
The storage device is segmented into multiple specialized components: front-end ASIC with processing cores for command decomposition, mid-end ASIC with LDPC engines for error correction, and back-end ASIC for I/O operations. This segmentation allows each component to be optimized for its specific function, achieving high database throughput while managing complexity through modular design
Solution Approach 2:
The front-end ASIC processing cores are designed to universally handle multiple database operations (select, insert, update, delete) and decompose various host commands. This multi-functionality allows a single component to perform diverse tasks, improving productivity without proportionally increasing overall device complexity
2Reliability
If traditional parity bit configuration is used, then storage capacity is maximized, but bit error rate is high and power consumption increases
Solution Approach 1:
The system changes the parity bit configuration parameter from traditional values to 33.3% parity overhead, which optimizes the balance between error correction capability and storage capacity. This parameter change reduces bit error rate while the modular ASIC architecture mitigates the capacity loss through efficient resource utilization
Solution Approach 2:
The patent implements redundancy through parity bits and error correction codes, creating copies of data information in encoded form. The 33.3% parity configuration creates sufficient copies to reduce bit error rate while the specialized LDPC engines efficiently process these redundancy bits without excessive power consumption
3Productivity
If database operations are processed on host system, then processing capability is sufficient, but data throughput between host and storage is limited
Solution Approach 1:
The front-end ASIC processing cores act as intermediaries between the host system and storage operations. These cores decompose host commands and initiate database operations directly on the storage device, enabling the storage device to function as an autonomous database system. This intermediary layer achieves high data throughput by eliminating the need for all processing to occur on the host while managing complexity through specialized hardware design
Data Source
AI summary
A method and apparatus for the increase of internal data throughput and processing capability for SSD's, to enable processing of database commands on an SSD. A front-end ASIC is provided with 256 to 512 RISC processing cores to enable decomposition and parallelization of host commands to front-end module (FM) ASICs that each in turn are coupled to multiple NVM dies, as well as processing of host database operations such as insert, select, update, and delete. Each FM ASIC is architected to increase parity bits to 33.3% of NVM data, and process parity data with 14 LDPC's. By increasing the parity bits to 33.3%, BER is reduced, power consumption is reduced, and data throughput within the SSD is increased.