Asynchronous Dataflow Interconnect Crossbar for Flexible Pipelining
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Solution Overview
Problem
Synchronous networks in programmable devices face limitations in pipelining due to clock jitter and skew, making it difficult to achieve functional correctness, while asynchronous networks offer flexibility but require handshaking and fan-out, which have their own disadvantages.
Innovation Solution
A compute dataflow architecture using an integrated circuit with an array of circuit tiles connected via interconnect tiles that include handshaking circuitry for asynchronous communication, forming a non-blocking crossbar to enable efficient data transfer without relying on clock signals, allowing for flexible pipeline lengths and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If synchronous networks are used to transfer data between CLEs, then data transfer can be performed each clock cycle, but pipelining is difficult to achieve due to clock jitter, clock skew, and the requirement that parallel paths must match in length
Solution Approach 1:
The synchronous network is segmented into multiple pipeline stages with pipeline registers inserted at strategic points. This segmentation allows the data path to be divided into manageable sections that can be independently timed, enabling pipelining while maintaining synchronous operation. Each segment can be optimized independently, and the pipeline registers act as synchronization points that absorb timing variations between parallel paths.
Solution Approach 2:
Pipeline registers are placed in advance at predetermined locations within the data path to pre-establish synchronization points. This preliminary placement of registration points allows parallel paths to be equalized in length before data flows through them, ensuring that all paths can be synchronized to the same clock edge without requiring dynamic adjustment during operation.
2Adaptability or versatility
If asynchronous networks are used to transfer data between CLEs, then pipelining can be achieved with different parallel path lengths and without clock dependency, but handshaking and fan-out mechanisms are required which increase complexity
Solution Approach 1:
Pipeline registers serve as intermediary elements between different pipeline stages, providing a standardized interface that simplifies the interaction between stages. These registers act as buffers that absorb the complexity of timing synchronization, allowing the rest of the pipeline to operate with simple combinational logic. The intermediary registers translate the complexity of asynchronous-like flexibility into a simpler synchronous framework.
Solution Approach 2:
The invention changes the timing parameter from fully asynchronous handshaking to synchronous clocked operation, while maintaining the functional flexibility of asynchronous pipelines. By using clocked pipeline registers with controlled enable signals, the system achieves variable path lengths and flexible pipelining without requiring complex handshaking protocols, thus changing the operational parameter from asynchronous to synchronous while preserving adaptability.
3Productivity
If highly pipelined designs are used to increase throughput in synchronous networks, then more pipeline stages can be implemented, but clock jitter and skew prevent functional correctness
Solution Approach 1:
The pipeline is segmented into multiple stages with pipeline registers inserted at each stage boundary. This segmentation breaks down the long combinational logic paths into shorter segments, reducing the impact of clock jitter and skew on any single stage. Each segment can be independently optimized to meet timing requirements, and the pipeline registers provide regeneration points that restore signal integrity and timing alignment.
Solution Approach 2:
Pipeline registers are preliminarily positioned at strategic locations within the data path to pre-establish timing alignment points. This preliminary placement ensures that all parallel paths are equalized in length and arrive at synchronization points simultaneously, preventing functional correctness issues before they occur. The registers are placed in advance based on static timing analysis rather than requiring dynamic adjustment.
Data Source
AI summary
An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.