Dataflow Graph Compiler for Heterogeneous SoC Programming
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Solution Overview
Problem
Existing systems for a System on a Chip (SoC) with a mix of programmable and hardened logic are cumbersome and difficult to parallelize, requiring detailed understanding of hardware components and communication between them, especially when expressing heterogeneous computations.
Innovation Solution
A method to implement a dataflow graph in a heterogeneous processing environment by receiving graph source code defining kernels and communication links, identifying constraints, and configuring the graph object during compilation to satisfy these constraints, allowing the compiler to automatically assign kernels to programmable or hardened logic blocks and select communication techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If hardware description language (HDL) or Open Computing Language (OpenCL) is used to write programs for a SoC with a mix of programmable and hardened logic, then the program can be compiled into bitstream and binary code for configuring the hardware, but the programming becomes cumbersome and difficult to parallelize
Solution Approach 1:
The patent introduces a dataflow graph as an intermediary representation between the high-level programming language and the heterogeneous hardware architecture. The graph source code defines computation nodes and communication links that are automatically mapped to the SoC's programmable and hardened logic blocks, eliminating the need for programmers to directly manage hardware configuration details while enabling efficient parallelization through the graph's inherent dataflow structure
Solution Approach 2:
The patent replaces the traditional mechanical approach of manually configuring hardware with automated compiler-based mapping. The compilation process automatically translates graph source code into appropriate bitstream and binary code configurations, substituting manual hardware configuration mechanics with automated software compilation mechanics that handle the complexity of mapping computations to heterogeneous hardware resources
2Productivity
If data-parallelism and thread-parallelism are used to express computations, then parallel processing can be achieved, but these techniques do not extend naturally to programmable logic where heterogeneous computations with different interfaces need to be expressed
Solution Approach 1:
The patent creates a universal dataflow graph framework that can represent both data-parallel and thread-parallel computations within a single paradigm. The graph nodes can represent different types of computations (programmable logic, hardened logic, memory operations) with unified syntax, allowing the same dataflow graph structure to express heterogeneous computations with different interfaces without requiring separate programming techniques for each parallelism type
3Manufacturing precision
If detailed understanding of programmable and software configurable hardened logic is required, then precise hardware configuration can be achieved, but the programming becomes cumbersome and difficult
Solution Approach 1:
The patent segments the programming task into two distinct layers: a high-level graph source code layer that defines computation logic independently of hardware details, and a compilation layer that handles the precise mapping to specific hardware resources. This segmentation allows programmers to work at the abstract graph level without needing detailed hardware knowledge, while the compiler handles the precise configuration of programmable and hardened logic blocks based on the graph's computational requirements
Data Source
AI summary
Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bitstream and/or binary code which configures programmable and non-programmable logic in a heterogeneous processing environment of a SoC to execute the graph. The compiler can also consider user-defined constraints when compiling the source code. The constraints can dictate where the kernels and buffers should be placed in the heterogeneous processing environment, performance requirements, data communication routes through the SoC, type of data path, delays, and the like.