Dataflow Graph Simulation via Threaded Kernel Assignment
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Solution Overview
Problem
Simulating a dataflow graph in a system on a chip (SoC) with mixed programmable and non-programmable logic is cumbersome due to the need for detailed understanding of hardware communication and the difficulty in parallelizing heterogeneous computations across different interfaces and synchronization primitives.
Innovation Solution
A method is described that involves receiving a graph specification defining kernels and communication links, assigning kernels to threads, identifying simulation components in a runtime library for heterogeneous communication protocols, and generating a simulation executable to simulate the dataflow graph in a heterogeneous processing environment, allowing for high-level expression of dataflow graphs without requiring detailed understanding of hardware implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If sequential source code or OpenCL is used to write programs for a SoC with mixed programmable and non-programmable logic, then the program can be written with detailed hardware understanding, but the programming becomes cumbersome and difficult to parallelize
Solution Approach 1:
The patent introduces a dataflow graph as an intermediary representation between the programmer and the heterogeneous hardware. The graph specification language allows programmers to describe computations and data flows without directly managing hardware interfaces, while the compiler automatically handles the complex mapping to programmable and non-programmable logic, enabling both ease of programming and effective parallelization
Solution Approach 2:
The patent replaces the manual mechanical process of writing sequential code with detailed hardware management by an automated compilation process. The compiler system automatically translates high-level dataflow graph specifications into optimized parallel execution code for heterogeneous hardware, substituting the manual coding mechanism with an automated compilation mechanism that handles parallelization
2Productivity
If data-parallelism and thread-parallelism are used to express computations, then parallel processing is achieved, but these techniques do not extend naturally to programmable logic where heterogeneous computations with different interfaces need to be expressed
Solution Approach 1:
The patent creates a universal dataflow graph framework that can represent both data-parallel and thread-parallel computations, as well as heterogeneous computations with different interfaces. The graph specification language and compiler provide a multi-functional system that handles diverse computation types through a unified representation, allowing the same framework to express regular array computations and irregular heterogeneous computations
3Reliability
If simulation of dataflow graph is performed before implementation on SoC, then design verification is enabled, but simulation is difficult due to parallelization requirements and heterogeneous communication protocols
Solution Approach 1:
The patent creates a software simulation copy of the dataflow graph that runs on standard processors before hardware implementation. This simulation copy uses the same graph specification language and compilation process, allowing design verification in a software environment without requiring complex parallelization or heterogeneous communication infrastructure, thus enabling reliable verification while avoiding simulation complexity
4Measurement precision
If detailed understanding of hardware communication is required, then precise control over communication is achieved, but the programming becomes cumbersome and difficult
Solution Approach 1:
The patent extracts the complex hardware communication details from the programmer's responsibility and handles them automatically in the compilation process. The compiler extracts communication requirements from the dataflow graph specification and automatically generates the appropriate communication code for heterogeneous interfaces, providing precise communication control without requiring programmers to understand or manually manage hardware communication protocols
Data Source
AI summary
Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges. A compiler converts the source code into a bit stream and/or object code which configures a heterogeneous processing environment of a SoC to execute the graph. Before implementing the dataflow graph on the SoC, the programmer may wish to simulate the dataflow graph. In one embodiment, each kernel in the dataflow graph is assigned a respective thread. Additionally, the simulator can include a runtime library for simulating the different types of communication links between the kernels. Even those these communication links are different protocols or have different semantics, using the simulation components in the library makes the different types of communication links composable so they can inter-operate in the same simulation environment.