Dataflow Graph Compiler for Heterogeneous SoC Kernel Mapping
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Solution Overview
Problem
Existing systems for SoCs with a mix of programmable and software-configurable hardened logic are cumbersome and difficult to parallelize, as they require detailed understanding of hardware components and communication between them, making it hard to express heterogeneous computations effectively.
Innovation Solution
A method for implementing a dataflow graph on a heterogeneous processing system by receiving graph source code, compiling it to assign kernels to programmable logic and data processing engines, and selecting communication types and synchronization techniques, allowing for independent hardware design and efficient data transfer between kernels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If hardware description language (HDL) or OpenCL is used to write programs for a SoC with a mix of programmable and hardened logic, then the system can be programmed to perform user functions, but the programming process becomes cumbersome and difficult to parallelize
Solution Approach 1:
The patent introduces a dataflow graph as an intermediary abstraction layer between the programmer and the heterogeneous hardware architecture. The graph source code defines kernels and communication links that are automatically mapped to the underlying hardware components, eliminating the need for programmers to directly manage hardware details while maintaining full control over programmable and hardened logic resources.
Solution Approach 2:
The patent segments the computation into discrete kernels that can be independently defined, compiled, and mapped to different hardware resources. Each kernel represents a separable computational unit that can be assigned to either programmable logic or hardened data processing engines, enabling automatic parallelization without requiring the programmer to manually manage parallelism.
2Productivity
If data-parallelism and thread-parallelism are used to express computations, then array processing can be performed, but these techniques do not extend naturally to programmable logic where heterogeneous computations with different interfaces need to be expressed
Solution Approach 1:
The dataflow graph framework provides a universal programming model that can express both data-parallel operations on arrays and heterogeneous computations with different interfaces through a single unified paradigm. The same graph source code can represent kernels that execute on either homogeneous data processing engines or heterogeneous programmable logic, automatically adapting to the target architecture.
3Reliability
If a user writes programs with detailed understanding of hardware components and communication, then precise control over hardware can be achieved, but the programming process becomes cumbersome and difficult
Solution Approach 1:
The patent uses graph source code as a software representation (copy) of the desired hardware computation pattern. This abstract representation is automatically translated into the actual hardware configuration through compilation, preserving the computational intent while eliminating the need for programmers to directly manipulate hardware details. The compiler maintains the precise mapping between the graph kernels and hardware resources.
Data Source
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AI summary
Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.