Configurable Dataflow Operator Circuits for Exascale Energy Efficiency

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Solution Overview

Problem

Exascale computing requires significant system-level floating point performance within a tight power budget, and classical von Neumann architectures face challenges in simultaneously improving performance and energy efficiency due to out-of-order scheduling, complex register files, and other structures, which lead to high energy costs.

Innovation Solution

A spatial array of processing elements connected by lightweight communication networks, where dataflow operators only process input data when available and there is space for output, eliminating control overheads and utilizing network dataflow endpoint circuits to perform dataflow operations instead of processing elements, allowing for direct execution of dataflow graphs and supporting high-radix multiplexing and demultiplexing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If classical von Neumann architectures are used to improve processing performance, then computational capability increases, but energy consumption increases significantly

Engineering Contradiction:

Improveprocessing performanceVSAvoidenergy consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The system segments processing functions into distributed dataflow operators across multiple processing elements, eliminating the need for complex centralized control structures like out-of-order scheduling and large register files that consume significant energy in von Neumann architectures

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Dataflow operators automatically process data when inputs are available and output space exists, eliminating the need for energy-intensive control overheads, scheduling logic, and status tracking mechanisms required in traditional processors

Inventive Principle:

Principle #25Self-service

2Productivity

If out-of-order scheduling and complex register files are implemented to improve performance, then instruction execution efficiency increases, but device complexity and energy cost increase

Engineering Contradiction:

Improveinstruction execution efficiencyVSAvoidcontrol structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts and removes complex control structures (out-of-order scheduling, large register files, branch prediction) from the processing elements, replacing them with simple dataflow operators that only require basic data routing and operation execution

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of having control logic manage data flow through complex scheduling, the system inverts the approach by having data flow automatically trigger operations when dependencies are met, eliminating the need for complex control structures

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS10469397B2Processors and methods with configurable network-based dataflow operator circuits

Publication Date: 2019.11.05 INTEL CORP

AI summary

Systems, methods, and apparatuses relating to configurable network-based dataflow operator circuits are described. In one embodiment, a processor includes a spatial array of processing elements, and a packet switched communications network to route data within the spatial array between processing elements according to a dataflow graph to perform a first dataflow operation of the dataflow graph, wherein the packet switched communications network further comprises a plurality of network dataflow endpoint circuits to perform a second dataflow operation of the dataflow graph.