Dataflow Architecture Processor for Low-Overhead Affine Transforms
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Solution Overview
Problem
Conventional CPUs and GPUs incur significant overhead due to dynamic reconfiguration and implicit instruction dependencies when performing affine transformations on images, which affects the efficiency and feasibility of training neural networks and other applications requiring large numbers of such transformations.
Innovation Solution
A statically reconfigurable dataflow architecture processor (SRDAP) performs N-dimensional affine transformations by statically mapping a dataflow program to its hardware, eliminating the need for dynamic instruction fetching and handling of implicit dependencies, and utilizing statically reconfigurable vector compute datapaths and memories for direct operand communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional CPUs and GPUs are used to perform affine transformations, then the transformations can be performed with flexible programming, but significant overhead is incurred due to dynamic reconfiguration and implicit instruction dependencies
Solution Approach 1:
The patent applies dynamics by making the processor statically reconfigurable through configuration data that defines the dataflow graph and computation structure. This allows the system to adapt to different affine transformation requirements while eliminating runtime dynamic reconfiguration overhead, resolving the contradiction between flexibility and efficiency.
Solution Approach 2:
The configuration data is loaded into configuration stores before execution begins, performing the reconfiguration action in advance. This preliminary setup eliminates the need for dynamic instruction fetching and handling during transformation execution, thereby improving productivity while maintaining adaptability through pre-defined configuration options.
2Adaptability or versatility
If dynamic instruction fetching is used in conventional processors, then programming flexibility is maintained, but overhead increases due to instruction dependency handling
Solution Approach 1:
The patent extracts the instruction fetching and dependency handling overhead by using a dataflow architecture where operations are triggered by data availability rather than sequential instruction execution. Configuration data directly defines the computation graph, eliminating the need for dynamic instruction fetching and reducing time loss.
3Productivity
If statically reconfigurable architecture is used, then overhead is reduced and throughput increases, but adaptability to different transformation types may be limited
Solution Approach 1:
The configuration data structure is designed to be universal, supporting multiple affine transformation types (rotation, scaling, shearing, translation) through a unified dataflow graph representation. This allows the statically reconfigurable processor to maintain high throughput while adapting to different transformation requirements through configurable parameters defined in the computation graph.
Data Source
AI summary
A computer-implemented method performs an affine transform over N dimensions using a dataflow architecture processor (DAP) comprising compute units and memory units interconnected by switches. The method includes mapping compute units into N groups corresponding to the N dimensions of the affine transform and statically reconfiguring each group to perform a dot product. Each group concurrently calculates one coordinate of an input pixel vector by performing a dot product between a respective row of the affine transform matrix and a vector of output pixel coordinates. Using the resulting input pixel coordinates, a first memory address is calculated to read a pixel value of an input image from the DAP memory units. The pixel value is then written to a second memory address corresponding to the output pixel coordinates. This method enables efficient parallel computation of affine transforms over multiple dimensions within a dataflow architecture.