Data Link Layer FEC and ARQ Parallel Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The series processing of Forward Error Correction (FEC) and Automatic Repeat Request (ARQ) in communication systems leads to bottlenecks, increasing Hybrid Automatic Repeat Request (HARQ) latency and impacting system bandwidth, as FEC processing is typically performed upstream from ARQ processing.
Innovation Solution
Moving FEC processing into the Data Link Layer to enable parallel processing with ARQ, allowing FEC and ARQ to occur simultaneously, and utilizing a receive buffer circuit to filter and expedite error-free data to upper OSI layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FEC processing is performed upstream from ARQ processing in series, then error correction is achieved, but HARQ latency increases and system bandwidth is reduced
Solution Approach 1:
The patent performs ARQ error detection before FEC error correction by placing ARQ processing downstream in the processing chain. This preliminary action allows the system to quickly identify errors using simpler ARQ checks before committing resources to more complex FEC processing, thereby reducing overall HARQ latency while maintaining error correction capability
Solution Approach 2:
The patent segments the error handling process into two distinct stages: first ARQ-based error detection at the data link layer, then FEC-based error correction. This segmentation allows each processing stage to operate independently and optimally, with ARQ providing quick rejection of obviously erroneous packets and FEC providing detailed correction for recoverable errors, thus reducing total processing time
2Reliability
If FEC processing is performed upstream from ARQ processing in series, then error correction is achieved, but system bandwidth is reduced
Solution Approach 1:
By performing ARQ error detection before FEC error correction, the system quickly identifies and rejects erroneous packets using simpler checks. This preliminary action prevents wasteful processing of corrupted data through the entire FEC pipeline, thereby improving system bandwidth utilization while maintaining error correction capability for recoverable errors
Solution Approach 2:
The patent segments error handling into ARQ detection and FEC correction stages, allowing parallel processing paths. This segmentation enables the system to handle error-free and erroneous packets through different optimized paths, improving overall system throughput and bandwidth efficiency while maintaining comprehensive error correction capability
Data Source
AI summary
Methods and devices for reducing the latency associated with retransmitting data packets are provided. A device used to receive data packets may include physical layer circuitry and data link layer circuitry communicatively coupled to the physical layer circuitry. The data link layer circuitry may include an Automatic Repeat reQuest (ARQ) processing circuit to send requests for retransmitting data packets. The data link layer circuitry may also include a Forward Error Correction (FEC) processing circuit to receive decoded data packets from the physical layer circuitry, to perform error correction on packets received by the physical layer circuitry, and to provide a correction status signal to the ARQ processing circuit indicating whether or not a particular decoded data packet received from the physical layer circuitry contains one or more incurable errors.