Data-Link Frame Triggers for Synchronized Cross-Chip Debug

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Solution Overview

Problem

Conventional communication systems transmit cross-chip triggers asynchronously with data, leading to increased latencies and inaccurate debug operations due to the use of sideband channels that are not synchronized with data transmission.

Innovation Solution

The method involves packing cross-chip triggers in-band within data frames at the data-link layer of the transmitter, ensuring synchronization with data transmission, allowing for synchronized receipt and processing at the receiver, and enabling reliable debug operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If cross-chip triggers are transmitted through sideband channels (general-purpose pins), then the communication channel can be simplified and triggers can be sent independently, but timing synchronization with data transmission is lost and latency increases

Engineering Contradiction:
Improvecommunication channel structureVSAvoidlatency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent merges the trigger transmission function with the data transmission function by embedding triggers within data frames at the data-link layer. This eliminates the need for separate sideband channels and pins, achieving both simplified channel structure and maintained timing synchronization through the unified data frame transmission mechanism.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If cross-chip triggers are transmitted through sideband channels, then trigger transmission can be independent of data, but debug operations become inaccurate due to asynchronous receipt

Engineering Contradiction:
Improvetrigger transmission independenceVSAvoiddebug operation accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

By combining triggers with data frames at the data-link layer, the patent ensures that triggers are transmitted synchronously with data, enabling accurate timing information to be preserved. This allows the receiving device to accurately determine when triggers occurred relative to data transmission, improving debug operation accuracy while maintaining the ability to transmit triggers independently through the same channel.

Inventive Principle:
Principle #5Merging (Combining)

3Device complexity

If general-purpose pins are used for triggers, then the pin structure is simpler, but timing with the communication channel cannot be maintained

Engineering Contradiction:
Improvepin structureVSAvoidtiming synchronization
Core Design Contradiction:
Device complexityVSStability of the object's composition

Solution Approach 1:

The patent makes data frames universal by enabling them to carry both data payload and trigger information. The data-link layer protocol allows data frames to serve dual purposes: transporting data and embedding triggers, thereby eliminating the need for separate dedicated trigger pins while maintaining timing synchronization through the unified transmission mechanism.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12477398B2Method and system for transmitting in-band cross-chip triggers to maintain high-speed interconnect
Publication Date: 2025.11.18 NVIDIA CORP
  • US12477398B2 patent drawing
  • US12477398B2 patent drawing
  • US12477398B2 patent drawing

AI summary

A system includes a link having one or more data paths and a device coupled with the link and including a data link (DL) transmitter and a buffer. The device is to write one or more bits corresponding to a operation to a first portion of a data frame in response to an indication, the data frame comprising a second portion comprising data. The device is to transmit the first portion and the second portion of the data frame via the one or more data paths in response to writing the one or more bits corresponding to the operation. The device is to store the data frame at the buffer in response to writing the one or more bits corresponding to the operation.