Datapath Circuit Segmentation for DSP Hard Functions
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Solution Overview
Problem
Traditional Digital Signal Processor (DSP) architectures are inefficient in executing computationally hard mathematical functions like logarithms, exponents, and square roots, as they are optimized for multiplication and addition, leading to high computational load and power consumption when handling these functions.
Innovation Solution
A datapath circuit combining a digital multiply and accumulate circuit (MAC) with a digital hardware calculator, where the MAC handles efficient multiplication and addition, and the calculator performs computationally hard functions using look-up tables and interpolation, allowing parallel execution and optimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional MAC structure is used for all computations, then multiplication and addition operations are efficient, but computationally hard functions (logarithms, exponents, division, square roots) consume excessive power and time
Solution Approach 1:
The datapath circuit is segmented into two distinct computational units: a traditional MAC structure for multiplication and addition operations, and a dedicated digital hardware calculator for computationally hard functions. This segmentation allows each unit to be optimized for its specific function, preventing the MAC from being overloaded with hard function computations that would consume excessive power and time.
Solution Approach 2:
A control unit acts as an intermediary that receives operation codes and directs them to the appropriate computational unit. When a hard function (logarithm, exponent, division, square root) is detected in the operation code, the control unit routes it to the digital hardware calculator; otherwise, it directs the operation to the MAC structure. This intermediary ensures optimal resource allocation and prevents power consumption issues.
2Productivity
If a customized digital state machine is built for a specific hard function, then that function executes rapidly, but the DSP lacks flexibility to execute other types of hard mathematical functions
Solution Approach 1:
The digital hardware calculator is designed as a universal unit capable of executing multiple types of computationally hard functions (logarithms, exponents, division, and square roots) through a single integrated structure. This multi-functional calculator eliminates the need for separate customized state machines for each function while maintaining rapid execution speeds for all supported operations.
Solution Approach 2:
The hardware calculator's functionality is dynamically controlled through operation codes that specify which mathematical function to perform. The control unit interprets these codes and configures the calculator's internal logic accordingly, allowing the same physical hardware to adapt its behavior for different computational tasks without requiring separate dedicated circuits for each function.
3Device complexity
If the MAC structure is used to compute hard mathematical functions, then the DSP can maintain architectural simplicity, but a large number of MAC cycles are consumed blocking other computations
Solution Approach 1:
The computational workload is segmented between two parallel processing units: the MAC structure handles multiplication and addition operations, while the digital hardware calculator handles computationally hard functions. This segmentation prevents the MAC from being blocked by hard function computations, maintaining high computational throughput for both operation types simultaneously.
Solution Approach 2:
The datapath circuit merges the traditional MAC structure with a dedicated digital hardware calculator into a unified architecture. Both units share common input memory elements and can operate in parallel on different operations, combining the strengths of both approaches to achieve high throughput without blocking.
Data Source
AI summary
A datapath circuit may include a digital multiply and accumulate circuit (MAC) and a digital hardware calculator for parallel computation. The digital hardware calculator and the MAC may be coupled to an input memory element for receipt of input operands. The MAC may include a digital multiplier structure with partial product generators coupled to an adder to multiply a first and second input operands and generate a multiplication result. The digital hardware calculator may include a first look-up table coupled between a calculator input and a calculator output register. The first look-up table may include table entry values mapped to corresponding math function results in accordance with a first predetermined mathematical function. The digital hardware calculator may be configured to calculate, based on the first look-up table, a computationally hard mathematical function such as a logarithm function, an exponential function, a division function and a square root function.