Datapath Reset Circuitry for Asynchronous Clock Domains
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Solution Overview
Problem
Existing systems fail to guarantee a clean reset of all datapaths within peripheral slave devices that have multiple asynchronous clock domains, as conventional reset protocols cannot synchronize and reset datapaths across multiple clock domains effectively.
Innovation Solution
The implementation of datapath reset circuitry and request/acknowledgement handshake circuitry in peripheral slave devices, which includes synchronizer circuits, multiplexers, and additional components to synchronize and coordinate reset requests across multiple clock domains, ensuring a clean reset and acknowledgement handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a simple Request/Acknowledgement protocol is used to reset peripheral slave devices, then the reset process is simple and fast, but it cannot guarantee that all datapaths within a peripheral slave device with multiple clock domains will be reset
Solution Approach 1:
The reset protocol is segmented into distinct phases: request phase, acknowledgment phase, and data transfer phase. Each phase has specific control signals and timing requirements, allowing the system to reliably reset all datapaths across multiple clock domains while maintaining a structured and manageable protocol complexity
Solution Approach 2:
The host device sends a reset request signal before initiating any data transfer, allowing the peripheral slave device to prepare its internal datapaths and clock domains in advance. This preliminary reset action ensures all domains are synchronized and ready for subsequent operations
2Reliability
If signals are synchronized across multiple clock domains using traditional synchronizer circuits, then metastability is prevented, but the circuit complexity increases with additional flip-flops and logic
Solution Approach 1:
The synchronizer circuit uses a universal two-stage flip-flop structure that can be applied to any signal crossing clock domains. This standardized approach prevents metastability while avoiding the need for complex domain-specific synchronizer designs, reducing overall circuit complexity
Solution Approach 2:
The patent introduces intermediate register stages that act as mediators between different clock domains. These registers buffer and synchronize signals without requiring complex direct synchronization logic, simplifying the overall circuit design while ensuring signal stability
3Adaptability or versatility
If a host-slave architecture with asynchronous clock domains is used, then each peripheral device can operate independently at its own clock frequency, but conventional reset protocols cannot guarantee clean reset of all datapaths
Solution Approach 1:
The peripheral slave device provides feedback acknowledgment signals to the host device to confirm that reset operations have been successfully completed in all clock domains. This feedback mechanism ensures reliable reset while maintaining the independence of each clock domain's operation
Solution Approach 2:
The patent merges the reset control mechanism with the existing Request/Acknowledgement handshake protocol. By combining reset functionality with the established communication framework, the system achieves reliable datapath reset across independent clock domains without sacrificing clock domain independence
Data Source
AI summary
Embodiments of improved systems and methods are provided herein to reset all datapath logic within a peripheral slave device having multiple clock domains. An embodiment of the disclosed method includes receiving a reset request from a host clock device to reset the peripheral slave device, synchronizing the received reset request to each peripheral clock domain included within the peripheral slave device, and using the synchronized reset request generated within each peripheral clock domain to reset datapath logic contained within that peripheral clock domain. As the datapath logic is being reset, the method further includes using the synchronized reset request generated within each peripheral clock domain to generate an acknowledgement for that peripheral clock domain, synchronizing the acknowledgements generated in each peripheral clock domain to a reference clock domain, and combining the synchronized acknowledgements into a single acknowledgement, which is supplied to the host clock device to complete the reset.