Direct Bonded Copper Assembly Layout for Thermal Dissipation

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Solution Overview

Problem

Existing electronic assemblies with direct bonded copper substrates face challenges in thermal performance, leading to potential failure of electronic components due to excessive heating from heat-generating components.

Innovation Solution

The electronic assembly incorporates a dielectric layer with metallic buses, islands, and strips isolated by dielectric barriers, along with a current shunt resistor and heat sink, to enhance thermal dissipation and current handling capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If heat-generating components are integrated into the electronic assembly, then functional capability is improved, but thermal performance deteriorates due to excessive heating

Engineering Contradiction:
Improvefunctional capabilityVSAvoidthermal performance
Core Design Contradiction:
Adaptability or versatilityVSTemperature

Solution Approach 1:

The substrate is segmented into multiple metallic layers (first metallic layer, second metallic layer) with dielectric layers in between, creating a multi-layer structure that distributes heat generation across different planes and improves thermal management capability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Dielectric layers are introduced as intermediary materials between heat-generating components and the substrate, and between different metallic layers, providing both electrical isolation and thermal management pathways

Inventive Principle:
Principle #24Intermediary (Mediator)

2Temperature

If additional heat dissipation structures are added, then thermal performance is improved, but device complexity increases

Engineering Contradiction:
Improvethermal performanceVSAvoiddevice complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The metallic layers serve dual functions: they provide electrical conductivity for current flow and act as heat dissipation pathways, eliminating the need for separate dedicated heat sinks and reducing overall device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the electrical conduction function and thermal conduction function into the same metallic structures, so that the metallic layers simultaneously carry current and dissipate heat, reducing the number of separate components needed

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The configuration improves thermal performance and current carrying capacity, maintaining components within operational temperature ranges and reducing the risk of failure.

Implementation Method 1

a first metallic bus overlying the dielectric layer, the first metallic bus having a bus width; a second metallic bus overlying the dielectric layer and generally parallel to the first metallic bus

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

heat-generating components, such as semiconductors, current measurement devices, or both that generate thermal loads that can result in heating of the substrate and circuit traces

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentEP3503181B1Electronic assembly on direct bonded copper substrate
Publication Date: 2025.12.17 DEERE & CO
  • EP3503181B1 patent drawingFigure 1
  • EP3503181B1 patent drawingFigure 2
  • EP3503181B1 patent drawingFigure 3

AI summary

A metallic island is disposed between a first metallic bus and a second metallic bus. The first metallic strip is isolated from the metallic island by a first dielectric barrier. At least a parallel portion of the first metallic strip is generally parallel to the first metallic bus, the second metallic strip isolated from the second metallic bus by a second dielectric barrier. Each first semiconductor terminals that are coupled to the first metallic bus and to the metallic island. Each second semiconductor has terminals coupled to the metallic island and to the second metallic bus.