DBC Substrate Recessed Metal Layer for Crack Mitigation
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Solution Overview
Problem
High voltages applied to power modules using Direct Bonded Copper (DBC) substrates cause high temperatures, leading to structural issues such as stress cracks between the DBC and dielectric layer structures, due to mismatched coefficients of thermal expansion, which conventional fabrication methods fail to adequately address.
Innovation Solution
A semiconductor device package design featuring a substrate with a dielectric layer and a metal layer having distinct thickness portions, where the second portion surrounds the first portion, and the second thickness is less than the first but greater than zero, created using a lithographic process to form a recessed structure that reduces stress cracks and allows for compact device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high voltages are applied to power modules using DBC substrates, then power output is improved, but stress cracks occur between the DBC and dielectric layer structures due to thermal expansion mismatch
Solution Approach 1:
The metal layer is divided into multiple portions with different thicknesses (first portion with greater thickness, second portion with lesser thickness). This segmentation allows different regions to handle stress differently, with the thinner second portion accommodating thermal expansion differences and reducing stress concentration that would lead to cracks under high power conditions.
Solution Approach 2:
Different portions of the metal layer are given different local properties through varying thickness. The first portion maintains greater thickness for electrical connectivity, while the second portion has reduced thickness to mitigate stress and prevent cracking in regions prone to thermal expansion mismatch with the dielectric layer.
2Ease of manufacture
If conventional fabrication methods are used, then manufacturing simplicity is maintained, but stress cracks between DBC and dielectric layer structures are not adequately addressed
Solution Approach 1:
The recessed structure is formed during the fabrication process itself, before the device operates under high power conditions. By creating the varying thickness profile in advance through selective etching, the structure is pre-configured to handle thermal expansion stresses, preventing cracks before they occur during operation.
3Ease of manufacture
If uniform thickness metal layer is used, then manufacturing is simpler, but stress concentration occurs leading to cracks
Solution Approach 1:
The previously uniform metal layer is segmented into regions of different thickness. This segmentation creates a gradient structure where stress can be distributed more effectively, preventing stress concentration that would occur with uniform thickness and thereby improving overall stress resistance.
Solution Approach 2:
The thickness parameter of the metal layer is changed across different portions rather than maintaining a constant value. This parameter variation optimizes the mechanical properties, allowing the structure to better withstand thermal and mechanical stresses while maintaining electrical functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The recessed structure effectively mitigates stress cracks and thermal expansion mismatch, resulting in a more reliable and compact semiconductor device package with improved thermal management and reduced material usage.
Implementation Method 1
stress cracks between the DBC and dielectric layer structures, due to mismatched coefficients of thermal expansion
Data Source
AI summary
Implementations described herein are related to an improved semiconductor device package for providing an electrical connection between one or more semiconductor die and one or more substrates. The one or more substrates includes a dielectric layer having a first side and a second side opposite the first side, and a first metal layer bonded to the first side of the dielectric layer, the first metal layer having a first portion and a second portion. The semiconductor device package can also include a semiconductor die disposed onto the first metal layer within the first portion of the first metal layer. In some implementations, the one or more conducting substrates includes a direct bonded copper (DBC) substrate, i.e., the metal is copper.