DBI Circuit for Semiconductor Data Bus Inversion
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Solution Overview
Problem
The existing 3D memory devices, such as High Bandwidth Memory (HBM), face challenges in data transfer speed due to the long time required for DBI calculation, which is necessary for reducing power consumption during data transmission, as it involves a large number of logic gates and requires a sufficiently long read clock cycle, thereby suppressing data transfer speed.
Innovation Solution
The proposed solution involves a DBI circuit with multiple DBI FIFO circuits and calculators that perform DBI calculations within one to three clock cycles, using pointer signals to latch and invert data bits, allowing for simultaneous processing of data bits across multiple clock cycles, thereby reducing the overall DBI calculation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If DBI calculation is performed using a large number of logic gates to reduce power consumption during data transmission, then power consumption is reduced, but data transfer speed is suppressed due to the long calculation time requiring sufficiently long read clock cycles
Solution Approach 1:
The patent divides the data bus into multiple segments (first data bus and second data bus) and performs DBI calculations separately for each segment using dedicated calculators. This segmentation allows parallel processing of DBI calculations, reducing the overall calculation time while maintaining the power-saving benefits of DBI operations.
Solution Approach 2:
The patent introduces a time dimension by allowing DBI calculations to span multiple clock cycles (one to three cycles) rather than requiring a single long cycle. Multiple calculators operate simultaneously on different data segments, effectively adding a parallel processing dimension that accelerates the overall calculation throughput.
2Measurement precision
If the read clock cycle is extended to complete DBI calculation, then accurate DBI calculation is achieved, but data transfer speed is reduced due to the longer cycle time
Solution Approach 1:
The patent segments the DBI calculation task across multiple clock cycles and multiple calculators, allowing each calculator to perform accurate calculations on its assigned data segment within shorter time windows. This maintains calculation accuracy while reducing the effective cycle time constraint.
Solution Approach 2:
The patent ensures continuous DBI calculation throughput by having multiple calculators operate in parallel across multiple clock cycles. While individual calculations may span one to three cycles, the overall system maintains continuous processing flow, preventing idle time and maintaining high data transfer speed.
3Productivity
If DBI calculation is performed within one to three clock cycles using multiple calculators, then data transfer speed is enhanced, but device complexity increases due to multiple FIFO circuits and calculators
Solution Approach 1:
The patent divides the data processing function into multiple dedicated calculators and FIFO circuits, each handling specific segments of the data bus. This segmentation enables parallel processing that achieves high data transfer speed while distributing the complexity across modular, manageable units rather than requiring a single complex calculation unit.
Solution Approach 2:
The patent creates universal DBI calculator units and FIFO circuit structures that can handle multiple data segments through parallel operation. These standardized multi-functional units reduce overall system complexity compared to having custom dedicated circuits for each function, as the same structural blueprint is replicated across multiple calculators.
Data Source
AI summary
Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.