DBI Circuit Selective Bit Inversion for Memory Power Reduction
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Solution Overview
Problem
Memory devices face challenges in minimizing power consumption, particularly due to the transmission of unnecessary bits during data bus inversion (DBI) operations, which lead to increased power usage.
Innovation Solution
A DBI circuit in memory devices is designed with processing components that generate combination data by combining read data and previous data, selectively inverting it based on comparisons, and outputting only necessary bits, minimizing power consumption by applying the DBI algorithm only to required bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DBI function is applied to all bits during read operation, then data transmission stability is improved, but power consumption increases
Solution Approach 1:
The patent extracts and processes only the necessary bits that require DBI function, separating them from unnecessary bits. The circuit identifies which bits need inversion based on comparison with previous data and applies DBI only to those specific bits, rather than processing all bits uniformly, thereby reducing power consumption while maintaining data stability.
Solution Approach 2:
The patent applies different processing quality to different bits: necessary bits undergo DBI processing for stability, while unnecessary bits are transmitted without inversion. This local differentiation optimizes power consumption by applying the DBI function only where needed rather than uniformly across all data bits.
2Use of energy by moving object
If DBI algorithm is applied to minimize bit transitions, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent segments the data processing into distinct functional blocks: a first processing component that generates combination data by comparing current and previous data, a second processing component that selectively inverts necessary bits based on comparison results, and a third processing component that handles unnecessary bits. This segmentation manages complexity by organizing functions into modular components.
Solution Approach 2:
The patent performs preliminary comparison between current read data and previous output data before the actual DBI processing. The first processing component pre-identifies which bits are necessary for DBI application by comparing data patterns, allowing the subsequent inversion stage to efficiently process only those bits without requiring complex real-time decision-making circuitry.
3Reliability
If all read data bits are processed through DBI, then data stability is maintained, but unnecessary bit transitions increase power consumption
Solution Approach 1:
The patent extracts and identifies unnecessary bits from the read data that do not require DBI processing. By separating these bits from necessary bits, the circuit avoids performing inversion operations on unnecessary data, thereby eliminating wasted energy while maintaining stability for the essential bits through selective DBI application.
Solution Approach 2:
The patent applies partial DBI action by processing only the necessary subset of bits rather than all read data bits. The circuit determines the minimum required processing by comparing current and previous data, applying DBI inversion only where needed to maintain stability, rather than performing excessive processing on all bits regardless of necessity.
Data Source
AI summary
A data bus inversion (DBI) circuit of a memory device includes a first processing component configured to generate first combination data by combining read data read from a memory cell region and previous data previously outputted from a data line, and generate second combination data by selectively inverting the first combination data depending on a result of comparing the first combination data and the previous data; and a second processing component configured to generate data to be outputted from the data line, by combining the second combination data and the previous data, wherein the second processing component generates bits of unnecessary bit positions in the data to be the same as bits of the unnecessary bit positions in the previous data.