Memory Controller DBI Decoding Without a Dedicated Control Pin
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Solution Overview
Problem
Conventional Data Bus Inversion (DBI) techniques require an additional control pin for memory devices with narrow interfaces, making DBI encoding impractical for devices with fewer than four data links, as the extra pin is burdensome and often not utilized.
Innovation Solution
The proposed solution uses a portion of the code-space provided by an error detection correction (EDC) code to indicate whether read data is DBI-encoded, eliminating the need for a dedicated DBI control pin by incorporating DBI circuitry within the memory controller's write and read circuitry to conditionally invert data bits based on threshold criteria.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate control pin is used for DBI encoding, then the DBI signal can be transmitted reliably, but the pin count increases making it impractical for narrow interfaces
Solution Approach 1:
The patent merges the DBI control signal with the existing EDC code by embedding the DBI indication within the EDC code-space. Specifically, the EDC code is designed to detect not only data errors but also to indicate whether DBI encoding was applied to the data, thereby combining two separate signaling functions into one unified code structure and eliminating the need for a dedicated control pin
Solution Approach 2:
The EDC code is extended to serve multiple functions: it continues to provide error detection and correction capabilities while simultaneously indicating whether DBI encoding was applied to the data. This multi-functional approach allows the same code structure to handle both error protection and DBI control signaling, reducing the overall pin requirement
2Use of energy by moving object
If DBI encoding is applied to narrow-width memory devices, then power delivery is improved, but the additional control pin burden makes it unusable
Solution Approach 1:
The patent combines the DBI control function with the EDC code structure, allowing narrow-width memory devices to implement DBI encoding without requiring additional control pins. The EDC code is designed to carry both error detection information and DBI indication, enabling power delivery optimization through DBI while maintaining pin efficiency
Data Source
AI summary
Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.