DBI Encoding for Flash Memory Error Detection
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Solution Overview
Problem
Conventional error correction codes (ECC) for flash memories, such as cyclic redundancy check (CRC), require significant area overhead and lead to bandwidth loss, making them impractical for NAND memory due to high implementation overhead and bandwidth loss, especially with CRC causing up to 25% overhead for each byte.
Innovation Solution
The implementation of Data Bit Inversion (DBI) encoding schemes, where a byte's bits are inverted if it has five or more 1s, ensuring only four or fewer 1s are present, allowing for error detection by setting a flag, which is used to prevent write operations when errors are detected, thereby avoiding system failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC schemes (CRC) are used for error detection, then error detection capability is improved, but area overhead increases significantly and bandwidth is reduced
Solution Approach 1:
The patent extracts only the essential error detection function from conventional ECC schemes, eliminating the need for redundant bits. By using a simple parity bit approach, the solution retains error detection capability while removing the excessive area overhead associated with full CRC implementations.
Solution Approach 2:
The patent changes the parameter of error detection from using multiple redundant bits (CRC) to using a single parity bit. This parameter change reduces the area overhead significantly while maintaining sufficient error detection capability for flash memory applications.
2Reliability
If conventional ECC schemes (CRC) are used for error detection, then error detection capability is improved, but bandwidth loss increases
Solution Approach 1:
The patent extracts only the essential error detection function, removing the bandwidth-consuming redundant bits. By using a single parity bit instead of full CRC, the solution maintains error detection while minimizing bandwidth loss in flash memory operations.
Solution Approach 2:
The patent changes the bandwidth parameter by reducing the number of transmitted bits from full byte CRC to a single parity bit. This parameter change significantly reduces bandwidth loss while maintaining sufficient error detection capability.
3Area of stationary object
If Data Bit Inversion encoding is applied, then area efficiency is improved and bandwidth is preserved, but implementation complexity increases
Solution Approach 1:
The patent applies bit inversion as a simple transformation of the data. Instead of adding complex error correction codes, the solution inverts the bits based on a simple criterion (number of 1s), which is computationally lightweight and easy to implement while achieving area efficiency.
Solution Approach 2:
The patent uses a simple, disposable-looking bit inversion mechanism that appears complex at first but resolves to a very simple implementation. The DBI encoding can be implemented with minimal hardware resources, making it a cost-effective solution for flash memory.
Data Source
AI summary
A circuit for detecting an error in a byte of data transmitted over a channel includes a controller having a first DBI encoder configured to perform a first DBI encoding on a received byte of data. The circuit also includes a channel configured to receive the encoded byte from the controller. The circuit also includes a non-volatile memory having a second DBI encoder and configured to (1) perform a second DBI encoding on the encoded byte received over the channel, (2) check a DBI flag for the byte after the second DBI encoding, and (3) determine that the byte of data contains an error when the DBI flag after the second DBI encoding is 1. If the byte contains an error then it can be concluded that the channel contains a defect. In case of an error a write operation to memory core can be stopped.