DRAM Data Bus Inversion Circuitry for Switching Noise Reduction
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Solution Overview
Problem
Conventional data bus inversion systems face inefficiencies in processing DBI bits and associated data, leading to unnecessary power consumption, current fluctuations, and noise, particularly due to simultaneous switching noise and IDD current spikes.
Innovation Solution
The implementation of a memory device that treats the DBI bit as a regular data bit, storing and processing it internally, and using a 10-bit data bus configuration to reduce switching noise and AC power consumption by complementary switching of data bits and the DBI# bit, eliminating the need for DBI converter and formatter logic during read and write cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional DBI converter and formatter logic is used to process data bits, then data bus inversion can be achieved to reduce simultaneous switching noise, but device complexity increases and conversion delays occur
Solution Approach 1:
The patent extracts the DBI# bit from the data processing path and treats it as a regular data bit stored in memory, removing the need for separate DBI converter and formatter logic circuits. This eliminates the complexity associated with dedicated DBI processing while maintaining the noise reduction benefit through complementary switching of the 10 bits.
Solution Approach 2:
The patent makes the memory circuitry universal by treating the DBI bit as a regular data bit that can be stored and retrieved like any other data. The same memory cells and circuitry that store regular data bits also store the DBI bit, eliminating the need for specialized DBI processing circuits and reducing overall device complexity.
2Object-affected harmful factors
If DBI converter and formatter logic is implemented, then data bus inversion functionality is achieved, but write and read speeds decrease due to conversion delays
Solution Approach 1:
The patent removes the DBI conversion step from the data path by treating the DBI bit as a regular data bit. During write operations, the DBI bit is stored directly in memory without conversion, and during read operations, it is retrieved directly without formatting, eliminating conversion delays and improving both write and read speeds.
Solution Approach 2:
The patent performs the DBI inversion operation in advance during the write operation when data is first stored in memory. The complementary switching pattern is established at write time, and the same pattern is maintained during read operations, eliminating the need for separate conversion operations and reducing overall processing time.
3Productivity
If all data bits switch in the same direction during bus transitions, then full data bandwidth is utilized, but current spikes and power consumption increase
Solution Approach 1:
The patent introduces asymmetry in the switching behavior by including the DBI bit in the complementary switching group. When 5 data bits switch in one direction, the DBI bit switches in the opposite direction, creating an unbalanced switching pattern that reduces simultaneous switching noise and current spikes while maintaining full data bandwidth utilization.
Solution Approach 2:
The patent uses the DBI bit as a counterweight to balance the switching activity of the 5 data bits. By ensuring that the DBI bit switches in the opposite direction when data bits switch, the patent creates a counterbalancing effect that reduces the net current spike and power consumption while maintaining the full 10-bit data bandwidth.
4Object-affected harmful factors
If DBI bit is processed through separate converter and formatter circuits, then proper inversion signaling is achieved, but chip area increases
Solution Approach 1:
The patent makes the memory circuitry universal by using the same memory cells, word lines, bit lines, and control logic to store and retrieve the DBI bit as are used for regular data bits. This eliminates the need for separate DBI converter and formatter circuits, reducing chip area while maintaining the simultaneous switching noise reduction benefit.
Solution Approach 2:
The patent merges the DBI bit processing into the regular data path by treating the DBI bit as a regular data bit. The DBI bit is stored in the same memory cells as data bits, accessed by the same word lines and bit lines, and controlled by the same control logic, consolidating the circuitry and reducing overall chip area.
Data Source
AI summary
Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.