DBI Signal Generation Circuit With Adder-Based Bit Counting
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Solution Overview
Problem
Existing apparatuses for generating a data bus inversion (DBI) signal in semiconductor integrated circuits are limited in area margin and integration due to the need for multiple counters and increased signal lines, leading to reduced power efficiency and increased current loss.
Innovation Solution
The apparatus includes a full adder, a half adder, and a DBI determining unit that generates a DBI signal based on the sums and carries from these adders, enabling the DBI signal when the number of data with a specific logic value exceeds half the input data, thereby reducing the number of elements and signal lines required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple counters are used to generate DBI signal, then the DBI signal generation function is achieved, but the occupied area and device complexity increase
Solution Approach 1:
The patent merges multiple counter functions into a single counter that counts both high-level and low-level data simultaneously. The counter generates first information when counting high-level data and second information when counting low-level data, eliminating the need for separate counters for each data type. This consolidation directly reduces the occupied area and device complexity while maintaining the DBI signal generation function.
Solution Approach 2:
The single counter in the patent performs multiple functions: it counts high-level data to generate first information, counts low-level data to generate second information, and both information types are used for DBI signal generation. This multi-functionality allows the system to achieve comprehensive data monitoring with fewer components, reducing the occupied area compared to using separate dedicated counters for each function.
2Reliability
If multiple counters and signal lines are used, then complete data monitoring is achieved, but the number of elements and signal lines increases
Solution Approach 1:
The patent combines the monitoring of high-level and low-level data into a single counter operation. The counter sequentially counts high-level data to generate first information and low-level data to generate second information, reducing the number of elements from multiple counters to a single counter. This merging reduces device complexity while maintaining complete data monitoring capability.
Solution Approach 2:
The patent discards the need for separate counters for high-level and low-level data by using a single counter that recovers its counting function for the other data type after completing one count. For example, after counting high-level data, the same counter is reused to count low-level data. This approach eliminates redundant elements while preserving the completeness of data monitoring through sequential operation.
3Productivity
If more data output buffers are used to handle more data, then data transmission capacity increases, but current loss and power consumption increase
Solution Approach 1:
The patent implements a feedback mechanism where the single counter provides first information about high-level data count and second information about low-level data count to the DBI signal generation unit. This feedback allows the system to dynamically determine when to enable DBI signal based on the actual data distribution, optimizing power consumption by activating DBI only when necessary (when high-level data count exceeds the threshold), thus reducing unnecessary current loss while maintaining high data transmission capacity.
Data Source
AI summary
An apparatus for generating a DBI signal in a semiconductor integrated circuit includes a full adder that includes data input terminals and a carry input terminal, each of which receives data, performs an operation on the received data, thereby outputting a sum and a carry. A half adder includes data input terminals, each of which receives data, performs an operation on the received data, thereby outputting a sum and a carry. A DBI determining unit determines a logic value of each of the data according to the sums and the carries that are transmitted from the full adder and the half adder, thereby outputting a DBI signal.