Transition-Minimized Data Bus Inversion Logic Circuit
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Solution Overview
Problem
Conventional Data Bus Inversion (DBI)-AC techniques do not effectively account for transitions in the DBI bit, leading to excessive power consumption and noise due to unoptimized bit transitions in data buses, particularly in systems with asymmetric power delivery networks.
Innovation Solution
The proposed method involves setting the DBI bit based on its previous value and considering the number of transitions to limit the total number of bit transitions to N/2, where N is the number of data bits, thereby minimizing power consumption and noise by avoiding unnecessary transitions, especially focusing on reducing 0→1 transitions in systems with asymmetry in power delivery networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional DBI-AC techniques are used to reduce transitions, then power consumption is reduced, but the DBI bit transitions are not accounted for leading to excessive transitions
Solution Approach 1:
The patent applies feedback by monitoring the current value of the DBI bit and using it to influence the decision for the next DBI bit value. The transition counting logic incorporates the previous DBI state to prevent unnecessary transitions, creating a closed-loop control system that optimizes transition reduction while maintaining data integrity.
Solution Approach 2:
The patent changes the parameter of transition counting by including the DBI bit itself in the count. Instead of only counting data bit transitions, the system now counts total transitions including the DBI bit, and uses this modified parameter to make inversion decisions that limit total transitions to N/2.
2Object-generated harmful factors
If the DBI bit is included in transition counting, then total transitions are limited to N/2, but the complexity of the DBI logic increases
Solution Approach 1:
The patent merges the DBI bit transition counting with the data bit transition counting into a single unified transition count. By combining these functions into one logic block that counts all transitions together, the patent reduces overall system complexity compared to having separate counting mechanisms for data bits and DBI bit.
Solution Approach 2:
The patent performs preliminary action by capturing the previous DBI bit value before the current inversion decision is made. This pre-capture of the DBI state allows the logic to anticipate and prevent unnecessary transitions in advance, simplifying the decision-making process for the current DBI bit value.
3Reliability
If transitions are reduced to minimize power, then power integrity improves, but asymmetric power delivery networks require optimized transition management
Solution Approach 1:
The patent applies asymmetry by recognizing that transitions in asymmetric power delivery networks have different impacts. The logic is designed to work effectively with asymmetric Vdd and Vss networks by optimizing the overall transition count, which inherently addresses the asymmetric nature of power delivery without requiring separate handling for each rail.
Data Source
AI summary
Circuits and methods for Data Bus Inversion (DBI) are provided. In one example, the immediately previous value of the DBI bit affects the next value of the DBI bit. Specifically, in some instances, the value of the DBI bit is held to the immediately previous value of the DBI bit to limit the total number of transitions on a data bus.