DBI Write Circuit With Precharged Global Bus for Lower DRAM Write Power
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Solution Overview
Problem
The challenge in the semiconductor memory field is to reduce power consumption while maintaining signal integrity and reliability, particularly in DRAM, where existing technologies face inefficiencies in data transfer and storage due to excessive flipping of the global bus during write operations, leading to high power consumption.
Innovation Solution
A write operation circuit is introduced that includes a serial-to-parallel conversion circuit, a data buffer module with NMOS transistors, a DBI decoding module, and a precharge module, which performs data flipping and decoding to minimize the number of global bus flips, thereby reducing current consumption. This circuit sets the initial state of the global bus high and uses DBI signals to determine whether to flip the data, optimizing power usage by ensuring more data bits are '1' during transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If data is transferred through the global bus during write operations, then data storage is achieved, but excessive flipping of the global bus increases power consumption
Solution Approach 1:
The patent applies data bus inversion (DBI) technique where the data signal is inverted before being placed on the global bus. By inverting the data pattern, the number of transitions (flips) on the global bus is reduced, thereby lowering power consumption while maintaining signal integrity through coordinated inversion at both transmission and reception ends
Solution Approach 2:
The patent changes the state parameter of the global bus by setting it to a high initial state through the precharge module before data transfer. This parameter change (setting bus state to high) combined with selective data inversion optimizes the switching activity and reduces dynamic power consumption during write operations
2Productivity
If the global bus is flipped frequently during data transfer, then data transfer completeness is ensured, but current consumption increases
Solution Approach 1:
The patent performs preliminary actions by precharging the global bus to a high state before data transfer and pre-calculating the DBI control signals. This preliminary preparation ensures that the bus is ready for data transfer with minimized subsequent switching, thereby improving transfer efficiency while reducing current consumption during the actual data transfer phase
3Use of energy by stationary object
If DBI decoding is implemented to reduce bus flips, then power consumption decreases, but circuit complexity increases
Solution Approach 1:
The patent segments the write operation circuit into distinct functional modules: serial-to-parallel conversion circuit, data buffer module, DBI decoding module, and precharge module. Each module performs a specific function, which simplifies the design and analysis of the overall system while achieving power consumption reduction through coordinated operation of these segmented components
Solution Approach 2:
The patent introduces a DBI control signal as an intermediary that mediates between the data buffer module and the global bus. This control signal coordinates the inversion operation, allowing the system to reduce bus flips and power consumption without requiring complex direct control logic between other components, thereby managing circuit complexity effectively
Data Source
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AI summary
At least provided by the embodiments of the present application is a write operation circuit, comprising: a serial-to-parallel conversion circuit, which is used for performing serial-to-parallel conversion on first DBI data of a DBI port so as to generate second DBI data for transmission by a DBI signal line, and generating input data of a data buffer module according to the second DBI data and input data of a DQ port; the data buffer module, which is used for determining according to the input data of the data buffer module whether to turn over a global bus; DBI decoding modules, which are used for decoding global bus data according to the second DBI data and writing the decoded data into a storage block, the decoding comprising determining whether to turn over the global bus data; and a pre-charging module, which is connected to a pre-charging signal line and used for configuring the initial state of the global bus as high. The technical solution of the embodiments of the present application can, under a Precharge pull-up architecture, achieve a reduction in the number of turnovers of a global bus to thereby greatly compress current and reduce power consumption.