Injection-Locked DBPLL Timing Calibration for Low Jitter
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Solution Overview
Problem
Injection-locked phase-locked loops (PLLs) face challenges in achieving accurate injection timing due to variations in process, supply voltage, and temperature, leading to increased deterministic, random, and period jitter, which persist even in improved designs with additional phase detectors.
Innovation Solution
An injection-locked digital bang-bang phase-locked loop (DBPLL) circuit that self-tunes to achieve proper injection timing and bandwidth optimization, using a bandwidth optimization circuit and injection timing calibration to minimize jitter across varying conditions, by generating coefficients for the digital loop filter and adjusting the digitally-controlled oscillator with an injection pulser and down-sampling circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If injection timing is adjusted to reduce jitter, then deterministic jitter and random jitter decrease, but the circuit becomes more sensitive to process, voltage, and temperature variations
Solution Approach 1:
The patent implements a feedback mechanism where the output of the bang-bang phase-frequency detector is used to control the digitally-controlled oscillator, creating a closed-loop system that automatically adjusts to maintain optimal injection timing despite PVT variations. This feedback loop enables the circuit to self-correct timing offsets without external intervention.
Solution Approach 2:
The patent employs a digitally-controlled oscillator whose frequency and phase can be dynamically adjusted through digital control signals. By changing the operating parameters of the oscillator based on feedback from the phase-frequency detector, the system adapts to PVT variations while maintaining low jitter performance.
2Measurement precision
If additional phase detectors are added to improve injection timing accuracy, then timing precision improves, but device complexity increases
Solution Approach 1:
The patent uses a single bang-bang phase-frequency detector that serves multiple functions: detecting phase errors, controlling the digitally-controlled oscillator, and enabling injection timing calibration. This multi-functional approach achieves high timing accuracy without requiring multiple specialized phase detectors, thereby avoiding increased circuit complexity.
Solution Approach 2:
The system performs self-calibration of injection timing using the same phase-frequency detector that operates during normal PLL function. The detector's output is reused to adjust the oscillator timing, eliminating the need for separate calibration hardware and reducing overall circuit complexity while maintaining high precision.
3Measurement precision
If injection timing offset increases, then deterministic jitter and random jitter increase abruptly, but achieving correct timing becomes more difficult under PVT variations
Solution Approach 1:
The patent implements a dynamic system where the oscillator's phase and frequency are continuously adjustable through digital control. This dynamic capability allows the system to adapt to PVT variations in real-time, maintaining optimal injection timing and preventing jitter from increasing even when environmental conditions change.
Solution Approach 2:
The closed-loop feedback mechanism continuously monitors phase errors and adjusts the oscillator timing accordingly. This active compensation prevents injection timing offset from increasing under PVT variations, thereby maintaining low deterministic and random jitter levels across different operating conditions.
Data Source
AI summary
A phase-locked loop circuit is disclosed. The circuit includes a digital bang-bang phase-locked loop (PLL) electrically connected to an input clock signal connection and an output clock signal connection, and a down-sampling circuit connected to the input clock signal connection. The circuit also includes a digitally-controlled delay line receiving an output of the down-sampling circuit, and an injection pulser receiving an output of the digitally-controlled delay line and connected to provide an injection pulse to a portion of the digital bang-bang phase-locked loop (PLL). The circuit further includes an injection timing calibration circuit connected to a control input of the digitally-controlled delay line. The circuit provides calibration of injection timing and bandwidth optimization, thereby reducing jitter in an output signal from the PLL.